This paper presents a combined power amplifier system consisting of a linear amplifier unit with a switchedmode (class D) current dumping stage arranged in parallel. With this topology, the fundamental drawback of conventional linear power amplifiers—the high loss—is avoided. Compared to a pure class D (switching) amplifier, the presented system needs no output filter to reduce the switching fr...

The class D amplifier is not well known in audio applications. Its excellent power ratio (greater than 90%) is the most important advantage. The MOS transistors switching power stage is able to drive a useful power up to 100W to the loud speaker. However, designing such an amplifier is more difficult than designing a classical class A or AB power amplifier. The distortion level is also slightly...

In modern wireless communication systems it is required that the power amplifier could operate with high efficiency, high linearity, and low harmonic output level simultaneously. To increase efficiency of the power amplifier, a switching-mode Class E mode technique can be applied. This kind of a power amplifier requires an operation in saturation mode resulting in a poor linearity, and therefor...

This paper presents the numerical design algorithm for the class-DE amplifier, taking into account optimized resonant inductor designs. The proposed design algorithm provides the element values for satisfying the class-E switching conditions. Simultaneously, the optimal inductors, which have a minimum volume for achieving the permissible power conversion efficiency, can be obtained. By carrying...

Background and Objectives: In this paper, a new design strategy was proposed in order to enhance bandwidth and efficiency of power amplifier. Methods: To realize the introduced design strategy, a power amplifier was designed using TSMC CMOS 0.18um technology for operating in the Ka band, i.e. the frequency range of 26.5-40GHz. To design the power amplifier, first a power divider (PD) with a ver...

In this paper, we present an exact analysis of class DE amplifier outside optimum conditions. We derive analytical expressions of waveform equations. By using waveform equations, we derive initial values of current and voltage, switching voltage and the slope of switching voltage, output voltage and power conversion efficiency in steady state. We denote the behavior of class DE amplifier outsid...

This paper presents the design of a high efficiency, low THD, 5.7GHz fully differential power amplifier for wireless communications in a standard 0.18μm CMOS technology. The power amplifier employs a fully differential class-E topology to achieve high power efficiency by exploiting its soft-switching property. In order to achieve high operating frequency, an injectionlocked oscillator is utiliz...

The layout design of hysteresis controlled switching-mode amplifier for fourth generation Long-Term Evolution (4G LTE) applications is presented in this paper. Those circuits are used in envelope amplifiers (EAs) architectures, which supply voltage to the transmitter’s power amplifier (PA). The proper layout design can help to improve the overall efficiency of EA, because most of the energy del...

Co-design of digital signal-processing (DSP) algorithms and power-amplifier characteristics can lead to improved efficiency and linearity through a variety of strategies including: predistortion, DSP control over bias conditions, particularly the power supply voltage, and DSP generation of digital input signals for switching amplifiers. This paper discusses several amplifier architectures that ...

a new output structure for class e power amplifier (pa) is proposed in this paper. a series lc resonator circuit, tuned near the second harmonic of the operating frequency is added to the output circuit. this resonator causes low impedance at the second harmonic. the output circuit is designed to shape the switch voltage of the class e amplifier and lower the voltage stress of the transistor. t...