As chip complexity keeps increasing in system-on-chip (SoC), the on-chip interconnect has become a critical issue for large-scale chip design. It has been proposed that the packet-switched network exchanging messages between intellectual property (IP) cores is a viable solution for the SoC interconnect problem. The design of the router in such network-on-chip (NoC) architectures is the key to h...

Here is the first set of exercises. These are intended to cover subject groups 1-4 of the SOC/DAM syllabus (R, SC, SD, ESL). These questions are styled as Tripos questions, with 20 marks each, and they largely involve repeating what was lectured. (In future years, questions that require a greater amount of creative thinking might be set). Full model answers and answer notes are available (for s...

Here is the second set of exercises. These are intended to cover subject groups 5-8 of the SOC/DAM syllabus (ABD, SFT, RD, E). These questions are styled as Tripos questions, with 20 marks each, but they largely involve repeating what was lectured. Tripos exam questions this year will be certainly be no harder than anything in these exercises. (In future years, questions that require a greater ...

Ivan S. Kourtev,† Ray R. Hoare,† Steven P. Levitan,† Tom Cain,† Bruce R. Childers,‡ Donald M. Chiarulli,‡ David Landis,¶ †Dept. of Electrical Engineering ‡Dept. of Computer Science ¶Pittsburgh Digital Greenhouse 348 Benedum Hall Sennott Square Regional Enterprise Tower University of Pittsburgh University of Pittsburgh 425 Sixth Avenue, Suite 1150 Pittsburgh, PA 15261 Pittsburgh, PA 15260 Pittsb...

729 Abstract— Power consumption during testing System-On-Chip (SOC) is becoming increasingly important as the IP core increases in SOC. We present a new algorithm to reduce the scan-in power using the modified scan latch reordering and clock gating. We apply scan latch reordering technique for minimizing the hamming distance in scan vectors. Also, during scan latch reordering, the don't care in...

Low power has developed as an important subject in today's and Kaijian Shi, “Low Power Methodology Manual for System on Chip Design”. Embedded Systems 1 (Politecnico di Milano AA 2014/2015) Kaijian Shi, "Low Power Methodology Manual: For System-on-Chip Design", Springer 2008. approach capturing lowpower design characteristics in earlier design stages. (1) M. Keating et al., Low Power Methodolog...

Hybrid wired/wireless on-chip network is a promising communication architecture for multi-/many-core SoC. For applicationspecific SoC design, it is important to design a dedicated on-chip network architecture according to the application-specific nature. In this paper, we propose a heuristic wireless link allocation algorithm for creating hybrid on-chip network architecture. The algorithm can e...

Advanced CMOS technology possibilities, power, communication and flexibility issues as well as the design gap are directing System-on-Chip (SoC) platforms towards Network-on-Chip (NoC) interconnected identical processing tiles (PT) such as the Montium processor [1]. It is broadly acknowledged that advanced technologies below 45nm come with significant yield and reliability problems, necessitati...

Due to continuous improvements of semiconductor technologies new challenges for the design of highly integrated system-on-chip (SoC) solutions have arisen. Systems-on-Chip provide an implementation platform for many applications, and will revolutionize the design of future electronic systems. In this contribution we focus on several important challenges and unsolved problems concerning SoC desi...