Although the new generations of FPGAs provide support for partial and dynamic configuration, the huge reconfiguration latency is still a major shortcoming of the current FCCMs . Software and hardware techniques (compiler optimizations, configuration prefetching) have been used in order to reduce the impact of the configuration overhead on the overall performance. Nevertheless, these techniques ...

A real-time detection algorithm for small space targets was presented based on FPGA and DSP, and the corresponding hardware was designed. With this system, the Video image, whose frame frequency reaches 40 Hz and the size reaches 512×512 pixels, could be processed in real-time application. Firstly, Max-Median filter was realized in FPGA to depress noise to solve the problem of mass computation ...

Abstract—Space-Time Adaptive Processing (STAP) algorithm has recently been used in Passive Bi-static Radars (PBR) because it removes the clutter and non-cooperative transmitter effectively making the target detection easy in harsh environments like air-ground. Realtime implementation of STAP is a very challenging task as it is computationally-intensive, time-critical and resource-hungry process...

In this paper, we target on architecture consisting of a processor and a field programmable gate array (FPGA), where the FPGA can be reconfigured in run-time to perform different tasks. Dynamic reconfiguration provides a performance/cost advantage over load-time configuration, but a good design methodology is essential. We describe a C-based design flow for the architecture. To address the perf...

The estimation of the Direction Arrival (DoA) is one most critical parameters for target recognition, identification and classification. MUltiple SIgnal Classification (MUSIC) a powerful technique DoA estimation. algorithm requires complex mathematical operations like computation covariance matrix input signals, eigenvalue decomposition signal peak search. All these processing make real-time re...

The amount of data in real-time, such as time series and streaming data, available today continues to grow. Being able analyze this the moment it arrives can bring an immense added value. However, also requires a lot computational effort new acceleration techniques. As possible solution problem, paper proposes hardware architecture for Typicality Eccentricity Data Analytic (TEDA) algorithm impl...

Intel® timing models provide a simple and easy way to verify the timing of FPGA designs without the need to perform full physical electrical extractions and simulations. The three different operating corners available for 65 nm and newer FPGAs provide a thorough coverage of the time delays within the recommended operating conditions. Introduction How can a designer accurately predict the time d...

Low cost imaging sensors and powerful embedded computers have taken the field of computer vision to new heights. One challenges that remains is shorten development time it takes target one’s algorithm hardware. This work details steps necessary use Model Based Design first simulate then a stereo rectification undistortion an FPGA system on chip hardware target. demonstrates what future FPGA-bas...

This White Paper points out the most significant issues which can be encountered during DO-254 compliant verification process for FPGA designs. It proposes the methods of saving development time during the functional verification process, reusing the work done during RTL simulation and performing the in-hardware at-speed testing in target FPGA devices assuring at the same time a high visibility...

This paper presents a machine vision system for real-time computation of distance and angle of a camera from a set of reference points located on a target board. Three different smart camera architectures were explored to compare performance parameters such as power consumption, frame speed and latency. Architecture 1 consists of hardware machine vision modules modeled at Register Transfer (RT)...