This paper presents a solution for the hardware implementation of EIA-709.1 Control Networking Protocol. It is the basic protocol of LonWorks systems that is widely used for the building system and the sensor system. The EIA 709.1 protocol has been implemented at the hardware level from physical layer to network layer to reduce the computing load on the CPU. VHSIC hardware description language ...

This paper presents reconfigurable hardware architecture for MWD (Minimum Weight Decoding) algorithm for network error correction, with high throughput on Field Programmable Gate Array (FPGA). Network Error Correction (NEC) is used for detecting and correcting the errors in noisy communication channels when multicasting a source message to a set of nodes. Minimum Weight Decoding (MWD) algorithm...

The cognitive radio system is proposed as an optimal way to improve the frequency underutilization. Spectrum sensing is the first and the essential function in this approach. A cognitive user must sense his environment to detect the unused channels, and then he can use the free channel without causing any interference to the primary user. In this article, an innovative technique is proposed for...

This study applies FPGA (Field Programmable Gate Arrays) technology to implement a motion controller for wafer-handling robot which has three-DOF (Degree of Freedom) motion. The proposed FPGA-based motion controller has two modules. The first module is Nios II processor which is used to realize the motion trajectory computation and the three-axis position/speed controllers. The second module is...

Designers face the challenge of specifying and implementing complicated mixed-technology systems. In order to better address mixed-signal designs, the VHDL-AMS and Verilog-AMS languages have been developed. These languages provide powerful capabilities to model and simulate behaviors in both the continuous and discrete time domains. Contemporaneously, the control systems community developed the...

Data protection is a severe constraint in the heterogeneous IoT era. This article presents hardware–software cosimulation of AES-128 bit encryption and decryption for edge devices using Xilinx system generator. Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) implementation algorithm done with ECB CTR modes loop unrolled finite-state machine (FSM) based architectu...

We present a real-time video and image acquisition system, which has important characteristics such as modularity, configurability, versatility, and low cost. This system was developed on the Altera DE2 Board ® using Verilog HDL ® (Hardware Description Language), VHDL ® (VHSIC Hardware Description Language) and Block Diagram as coding languages. The proposed system architecture was applied for ...

In this paper a new background subtraction algorithm was developed to detect moving objects from a stable system in which visual surveillance plays a major role. However background subtraction in crowded scenes remains challenging especially when a large number of foreground objects move slowly. Among all existing algorithms it was chosen because of low computational complexity which is the maj...

Multi Valued Logic [MVL] is emerging as a promising choice for future computing technology. MVL has seen major advancement in the recent past due to several advantages offered by them over the binary logic, thus making it a thrust area for further research. The instruction set of the processor is its inherent entity. This paper presents design and implementation of an efficient instruction set ...

The underlying nature of adiabatic circuits is most accurately characterized at the circuit level as it for traditional technologies. In order to scale system designs logic technologies, modeling necessary. Logic models can facilitate design, development, and verification large digital systems that may be infeasible using simulators. Adiabatic powered with a four stage power clock consisting id...