Traditional improvements in packet switch architecture aimed at increasing switch performance in terms of utilization, fairness and QoS. This paper focuses on improving architecture to achieve implementation feasibility of terabit aggregate data rates while maintaining such performance. Terabit class shared-memory switch chips are simple in concept but are a challenge to build due to the memory...

Unmanned Aircraft Systems (UASs, commonly known as "drones") have proven to be useful as a platform for remote sensing (RS), that is the acquisition of information about objects, areas or phenomena from a distance, without making physical contact. Benefits are the operational flexibility, the possibility to be used in challenging situations and the higher spatial and temporal resolution of acqu...

Input queuing switch architectures must be controlled by a scheduling algorithm, which solves contentions in the transfer of data units from inputs to outputs. Several scheduling algorithms were proposed in the literature for switches operating onfied-size data units. In this paper we consider the case of packet switches, i.e., devices operating on variablesize data units at their interfaces, b...

Input queuing switch architectures must be controlled by a scheduling algorithm, which solves contentions in the transfer of data units from inputs to outputs. Several scheduling algorithms were proposed in the literature for switches operating on fixed-size data units. In this paper we consider the case of packet switches, i.e., devices operating on variablesize data units at their interfaces,...

Cell scheduling has received extensive attention. Most recent studies, however, focus on achieving a 100% switch throughput under the uniform arrivals. As the demand for quality of service increases, two important goals are to provide predictive cell latency and to reduce the output burstiness. This paper presents a new scheduling algorithm, Worst-case Iterative Longest Port First (WiLPF), whic...

High-performance input queued switches achieve good performance with low cost. However, with the appearance of optical techniques, the line rate is much higher than before. Scheduling algorithms require not only good performance in delay and stability but fast speed and simple implementation as well. A variety of scheduling algorithms for Virtual Output Queuing (VOQ) packet switch architecture ...

The behavior of the ideal General Processor Sharing (gps) discipline and di erent per-VC queuing algorithms approximating this ideal scheme, namely the Self Clocked Fair Queuing, the Packet by packet Generalized Processor Sharing, and the Virtual Starting Time disciplines, are studied in this paper via simulation. We speci cally consider a simple simulation con guration involving two Constant B...

InfiniBand is a new switch-based standard interconnect for communication between processor nodes and I/O devices as well as for interprocessor communication. InfiniBand architecture allows switches to support up to 15 virtual lanes per port for data traffic. To route packets through a given virtual lane (VL), packets are labeled with a certain service level (SL) at injection time, and SLtoVL ma...

We describe an eecient fair queuing scheme, Leap Forward Virtual Clock, that provides end-to-end delay bounds similar to WFQ, along with throughput fairness. Our scheme can be implemented with a worst-case time O(loglog N) per packet (inclusive of sorting costs), which improves upon all previously known schemes that guarantee delay and throughput fairness similar to WFQ. Interestingly, both the...

Network-on-chip (NoC) offers a scalable and flexible communication infrastructure for many-cores systems. Buffers in router is used fine-grain flow control Quality of Service (QoS), yet it the major contributor area power consumption. In this paper, we propose hybrid buffer design with SRAM Spin-Torque Transfer Magnetic RAM (STT-RAM) NoC leveraging novel architecture combined Virtual Channel (V...