Systems-on-Chip (SoCs) and Chip Multiprocessors (CMPs) have strong global communication requirements, and networks-on-chip (NoCs) have been proposed as a scalable solution to overcome these communication challenges. This work explores the application of NoCs in both SoCs and CMPs. For SoCs, our work considers the application-specific NoC architecture design problem in a 3D environment. We prese...

A Midimew-connected Mesh Network (MMN) is a minimal distance mesh with wrap-around links network of multiple basic modules (BMs), in which the BMs are 2D-mesh networks that are hierarchically interconnected for higher-level networks. In this paper, we present the architecture of the MMN, addressing of node, routing of message, and evaluate the static network performance of MMN, TESH, mesh and t...

On single silicon chip, the growing availability of number of resources is enforcing the designers to come up with mechanisms for effective and efficient management of these resources on a chip. Network-on-Chip (NoC) is used for highspeed inter-node communication inside a System-on-Chip (SoC). The routing algorithm is one of the key components in NOC architecture that decides the performance of...

Nowadays lots of processing elements should be placed on a single chip because of ever complexity of applications. In order to connect this number of processing elements, providing a interconnection infrastructure is essential. Network on Chip (NoC) is used as an efficient architecture for chip multiprocessors, which brings a reasonable performance and high scalability. A relevant challenge in ...

The Adapteva Epiphany many-core architecture comprises a scalable 2D mesh Network-on-Chip (NoC) of low-power RISC cores with minimal uncore functionality. Whereas such a processor offers high computational energy efficiency and parallel scalability, developing effective programming models that address the unique architecture features has presented many challenges. We present here a distributed ...

Intellectual property (IP) core-to-node mapping is an important but intractable optimization problem in Network-on-Chip (NoC) application design. In this paper, we present an approach to map cores onto hierarchical NoC architecture which consists of two levels. The top-level interconnection network is realized by a 2D mesh of communicating routers, and a tree based topology is used at the secon...

Massive multi-core embedded processors with network-on-chip (NoC) are becoming common in real-time systems. These architectures benefit real-time scheduling of tasks and provide higher processing capability due to abundance of cores. The core-to-core communication can be leveraged by adopting message passing to further increase system scalability. Despite these advantages, multicores pose predi...

Abstract Applications running in a large and complex manycore system can significantly benefit from adopting the dataflow model of computation. In execution environment, thread run only if all its required inputs are available. While potential benefits large, it is not trivial to improve resource utilization energy efficiency by focusing on models (i.e., ways specifying how threads adhering com...

Network-on-Chip (NoC) based many-cores are becoming popular due to their high scalability compared to traditional bus-based architectures. However they still lack software tailored to their specificities. In this paper we propose several techniques for tailoring and combining barrier synchronizations in order to take advantage of the 2D-meshed NoCs. Experimental results show that our combined b...