This paper presents a new method to reduce consumption power in flash ADC in 65nm CMOS technology. This method indicates a considerable reduction in consumption power, by removing comparators memories. The simulations used a frequency of 1 GHZ, resulting in decreased consumption power by approximately 90% for different processing corners. In addition, in this paper the proposed method was desig...

We demonstrate a low-power wireline transmitter with 2-tap pre-emphasis in which serialization is achieved by toggling serializer with data transition information extracted from parallel input data. This novel technique of serialization provides significantly reduced power consumption since it does not need the short pulse generation block required in the conventional serializer. In addition, t...

Today, given the extensive use of convertors in industry, reducing the power consumed by these convertors is of great importance. This study presents a new method to reduce consumption power in Flash ADC in 65nm CMOS technology. The simulation results indicate a considerable decrease in power consumption, using the proposed method. The simulations used a frequency of 1 GHZ, resulting in decreas...

This paper focuses on the DC noise margin analysis and read/write failure analysis of the proposed 8T low power SRAM cell. In the proposed structure two voltage sources, one connected with the Bit line and the other connected with the Bit bar line for reducing the voltage swing during the switching activity. These two extra voltage sources will control the voltage swing on the output node and i...

This paper presents the design and evaluation of a new SRAM cell made of nine transistors (9T). The proposed 9T cell utilizes a scheme with separate read and write wordlines; it is shown that the 9T cell achieves improvements in power dissipation, performance and stability compared with previous designs (that require 10T and 8T) for low-power operation. The 9T scheme is amenable to small featur...

This paper proposes an embedded TEC BCH scheme for ReRAM array, which is capable of low access time and uniform error distribution. The high speed decoder with SBSA proposed a fully-parallel architecture. An optimized adaptive correction approach utilized to reduce the power consumption. Furthermore, composite field arithmetic used minimize logical size. For performance evaluation, implemented ...

Single event upsets (SEU) produced by heavy ions in SOI CMOS SRAM cells were simulated using a mixed-mode approach, that is, two-dimensional semiconductor device simulation by TCAD tool coupled with circuit SPICE simulator. The effects of parasitic BJT and particle strike position on the SOI CMOS SRAM cells upset for transistor length scaling from 0.25 um to 65nm are presented.

We analyze a modern-day 65nm MOSFET technology to determine its electrical characteristics and intrinsic ballistic efficiency. Using that information, we then predict the performance of similar devices comprised of different materials, such as high-k gate dielectrics and III-V channel materials. The effects of series resistance are considered. Comparisons are made between the performance of the...