in this paper, a new high dynamic range digitally-controlled oscillator (dco) for all-dpll systems is proposed. the proposed dco is based on using a δς modulator as a digital-to-analog converter. using δς dac can provide a very high resolution (18-bit) control on the dco. the δς dac output is a 2-level pulse signal that needs to be filtered for cancelling the out of band shaped noise. the used ...

In this article, we introduce a fractional-N all-digital phase-locked loop (ADPLL) architecture based on single LC-tank, featuring an ultra-wide tuning range (TR) and optimized for ultra-low area in 10-nm FinFET CMOS. Underpinned by excellent switches the technology, high turn-on/off capacitance ratio of LC-tank switched capacitors, addition to adjustable magnetic coupling technique, yields alm...

This paper presents an ultra-lower-power (ULP) digital-to-time-converter (DTC)-assisted fractional-N all-digital phase-locked loop (ADPLL) suitable for IoT applications. A proposed hybrid time-to-digital converter (TDC) extends the vernier-TDC input range with little power overhead in order to overcome stability issue conventional architectures. The TDC also facilitates a background gain calibr...

This article presents a low-power fractional- ${N}$ all-digital phase-locked loop (ADPLL) employing reference-waveform oversampling (ROS) phase detector (PD) that increases its effective rate four times, thus leading to lower jitter a...

This paper presents a self-calibration circuit to correct the non-monotonic response in the cascading digitally controlled oscillator (DCO). The proposed calibration circuit can solve the non-monotonic problem when the coarse-tuning control code is changed. The proposed DCO implemented with a standard performance 65nm CMOS process can output frequency ranges from 58.7 MHz to 481.6 MHz. And the ...

This paper presents a hardware implementation of a fully synthesizable, technology-independent clock generator. The design is based on an ADPLL architecture described in VHDL and characterized by a digital controlled oscillator with high frequency resolution and low jitter. Frequency control is done by using a robust regulation algorithm to allow a defined lock-in time of at most eight referenc...