in this paper, a high speed delay-locked loop (dll) architecture ispresented which can be employed in high frequency applications. in order to design the new architecture, a new mixed structure is presented for phase detector (pd) and charge pump (cp) which canbe triggered by double edges of the input signals. in addition, the blind zone is removed due to the elimination of reset signal. theref...

this paper proposes a new method for parameter estimation of distorted single phase signals, through an improved demodulation-based phase tracking incorporated with a frequency adaptation mechanism. the simulation results demonstrate the superiority of the proposed method compared to the conventional sogi (second-order generalized integrator)-based approach, in spite of the dc-offset and harmon...

Phase locked loops (PLL) and delay locked loops (DLL) play an important role in establishing coherent references (phase of carrier and symbol timing) in digital communication systems. Fully digital receiver including digital carrier synchronizer and symbol timing synchronizer fulfils the conditions for universal multi-mode communication receiver with option of symbol rate setting over several d...

Sinusoidal transform coding (STC) techniques model speech as the sum of sine-waves whose frequencies, amplitudes and phases are specified at regular intervals. To achieve a low-bit rate representation, only the spectral envelope is encoded and the phases are regenerated according to a minimum phase assumption. In this paper, the inaccuracy of the minimum phase model is demonstrated. It is shown...

Radar Signal Processing has been an interesting area of research for realization of programmable digital signal processor using VLSI design techniques. Digital Signal Processing (DSP) algorithms have been an integral design methodology for implementation of high speed application specific real-time systems especially for high resolution radar. CORDIC algorithm, in recent times, is turned out to...

Figure 12: a) High-level block diagram of the segmented quantizer; b) quantization block details; c) signal processing model .. Figure 16: Estimated power spectra of a) the quantization noise sequences, and b) the running sums of the quantization noise sequences of the first-order ∆Σ modulator and the segmented quantizer presented in Section IV before and Ian Galton supervised the research whic...

Frequency synthesis is one of the most important and most actively researched subjects in the field of VLSI mixed-signal circuit design. Among the existing techniques in this area, phase locked loop fractional architecture is a widely used one for generating frequencies which are not integer multiple of the input reference frequency. Flying-Adder architecture is an emerging technique which is b...

The realization of a digital phase-locked loop (DPLL) requires to choose a suitable phase detector and to design an appropriate loop filter; these tasks are commonly nontrivial in most applications. In this paper, the phase detector is examined, and a simple model is given to describe the characteristics of the timing function. The DPLL system is then formulated as a state estimation problem; t...

The evolution of CMOS technology demands new approaches to implement radio-frequency integrated circuits. This paper presents two digital-intensive frequency synthesizers implemented in 65-nm CMOS: a digital period frequency synthesizer and an all-digital phase-locked loop. The experimental circuits cover frequency ranges of 0.1 4.3 GHz and 2.7 6.1 GHz.