In this paper, a novel architecture for asynchronous analog-digital conversion is presented, designed using the NULL Convention Logic (NCL) paradigm. This analogto-digital converter (ADC) employs successive approximation and a one-hot encoded masking technique to digitize analog signals. The architecture scales readily to any given resolution by utilizing the one-hot encoded scheme to permit id...

A radix-based digital self-calibration technique for multistage analog-to-digital converter(ADC) is presented. This technique can correct errors due to capacitor mismatch and finite opamp gain. The equivalent radix of each stage is extracted by measuring the discontinuity on the ADC transfer curve and iteratively adjusting the equivalent radix to minimize this discontinuity. A much more accurat...

A high-speed low-power flash analog-to-digital converter is designed and optimized in a 0.13μm CMOS technology. The ADC consumes 65mW with a supply voltage of 1.2V at 1.2G samples per second. Static DNL and INL are 0.1 LSB and 0.2LSB respectively. The figure of merit shows 1.3pJ per conversion step. The simulation result of the full flash ADC shows improvement in nonlinearity and power dissipat...

The method of testing points generation for identification and correction of integral nonlinearity of high performance ADC is developed. The proposed method is based on averaging all voltages of multi-resistors voltage divider. The main idea of proposed method is in comparison results of analog to digital conversion obtained on different ranges of tested ADC for the same input signals. It is in...

In a Digital Pixel Sensor (DPS), each pixel has an ADC, all ADCs operate in parallel, and digital data is directly read out of the image sensor array as in a conventional digital memory [1]. The DPS architecture offers several advantages over analog image sensors including better scaling with CMOS technology due to reduced analog circuit performance demands and the elimination of column fixed-p...

The continued drive toward technology scaling in VLSI design has provided greater integration levels in silicon chips. Thanks to the reduction in minimum feature size and the corresponding decrease in power supply voltage, digital circuits have benefited from savings in area and power consumption. This approach presents a number of challenges in Complementary Metal-Oxide Semiconductor (CMOS) an...

We consider analog to digital (A/D) conversion, based on the quantization of coefficients obtained via the projection of a continuous time signal over a set of basis functions. The framework presented here for A/D conversion is motivated by the sampling of an input signal in domains which may lead to significantly less demanding A/D conversion characteristics, i.e., lower sampling rates and low...

Hybrid filter bank analog-to-digital converters (ADCs) have been proposed as a candidate for high-speed, high-resolution analog-to-digital conversion. It is a generalization from time-interleaved ADCs, but it has the advantage that the mismatch errors inherent in parallel converters are attenuated by the filters. This paper gives an overview of hybrid filter bank ADC analysis and design. Furthe...

This paper describes a technique for digital error correction in pipelined analog-digital converters. It makes use of a slow, high resolution ADC in conjunction with an LMS algorithm to perform error correction in the background during normal conversion. The algorithm will be shown to correct for errors due to capacitor ratio mismatch, finite amplifier gain and charge injection within the same ...