As far as very deep sub-micron SOC design is concerned, integrated analog and RF parts on chip induce EMI noise through strong current variations. It has been proved that asynchronous circuits provide an efficient means of reducing current variations when compared to synchronous ones. Given this context, we proceed in two steps. On the one hand, we determine and quantify the current activity in...

Asynchronous logic design has been around for decades. However, only recently has it gained any commercial success. Research has focused on a wide variety of uses, from microprocessor design to low power circuits. The fact that design tools and designer experience are geared more towards synchronous circuit design has limited the acceptance and popularity of asynchronous design. The JBits API p...

We present a novel asynchronous RSFQ digital circuit, Test-Timed RSFQ digital circuit and system(TT), in this paper. With this asynchronous approach, data is transferred in a delay-insensitive fashion to avoid the overhead of global clock distribution and the timing uncertainty. According to the scheme, the timing signal of the logic module is generated by a test logic module. The delay module ...

In this paper we illustrate the application of a synthesis procedure used for timed asynchronous circuits to the design of synchronous circuits. In addition to providing a uniform synthesis approach, our procedure results in circuits that are significantly smaller and faster than those designed using the synchronous design tool SIS. .

Asynchronous rather than synchronous interconnect has been a promising alternative for a large scale system to remove significant problems caused by global clock trees. Considering the vulnerability of asynchronous circuit to hazards, in this paper we investigate the occurrence of deadlocks on asynchronous 2-phase interconnect. Finally we explore the space of fault tolerance in the 2-phase inte...

This paper considers the general problem of the synthesis of asynchronous combinational and sequential circuits based on the assumption that gate delays may be unbounded and that line delays are suitably constrained. Certain problems inherent to circuit realizations with unbounded gate delays are discussed and methods of solving them are proposed. Specific synthesis techniques are presented for...

IT OWES US GREAT PLEASURE to present this special issue on asynchronous circuits and systems. The recent surge of interest in asynchronous circuits came about after an increase in VL.9 communication applications and the current push toward achieving higher performance at lower power and design cost. Most of the recent literature on this topic, however, comes from academia and tends to be quite ...

Article history: Received 10 March 2015 Received in revised form 20 March 2015 Accepted 25 March 2015 Available online 10 April 2015

Even in the absence of clocks, time bounds on the duration of actions enable the use of time fordistributed coordination. This paper initiates an investigation of coordination in such a setting. A newcommunication structure called a zigzag pattern is introduced, and shown to guarantee bounds on therelative timing of events in this clockless model. Indeed, zigzag patterns are shown t...