A general design technique for achieving single faulttolerant asynchronous sequential circuits is described. The design procedures apply over a large range of fault conditions and are extremely easy to use. Generally, less than three times the logic required for a single copy is needed to achieve single fault tolerance. In addition to fault tolerance, real time fault detection is easily achieve...

This paper presents a switch-level test generation system for synchronous sequential circuits in which a new algorithm for switch-level test generation and an existing fault simulator are integrated. For test generation, a switch-level circuit is modeled as a logic network that correctly models all aspects of switch-level behavior. The time-frame based algorithm uses asynchronous processing wit...

The theory θ presented here is the smallest theory in the temporal logic TLB [10] that all distributed systems, according to our definition of a distributed system, must satisfy. θ is an instance of the classical modal logic S4.2. The central theorems of θ are stated here without proof. Proofs will appear in [10]. Logics like TLA [14] and TLRCS [18] are used for specifying computer programs and...

Abstract Hyperproperties are properties of computational systems that require more than one trace to evaluate, e.g., many information-flow security and concurrency requirements. Where a property defines set traces, hyperproperty sets traces. The temporal logics HyperLTL HyperCTL* have been proposed express hyperproperties. However, their semantics synchronous in the sense all traces proceed at ...

It has recently been shown that both asynchrony and perfect synchrony are needed for the speciication of complex reactive systems and a paradigm called Communicating Reactive Processes (CRP) was proposed towards such a uniication. The paradigm consists of a network of perfectly synchronous nodes communicating asynchronously. This paper addresses the implementation issues of such paradigms and d...

This paper shows how the application of a CMOS ternary logic is useful in the realisation of Delay Insensitive (01) asynchronous circuits. It is shown that fully DI asynchronous circuits are obtained with a ternary handshake protocol which employs the third logic level as idle state of the asynchronous interface. The advantages obtained are a dramatic reduction of the communication requirement ...