This paper presents the impact of multiple-detect test patterns on outgoing product quality. It introduces an ATPG tool that generates multiple-detect test patterns while maximizing the coverage of node-tonode bridging defects. Volume data obtained by testing a production ASIC with these new multipledetect patterns shows increased defect screening capability and very good agreement with the bri...

It has been observed that SAT formulae derived from ATPG problems are eeciently solvable in practise. This seems counter-intuitive since SAT is known to be NP ? Complete. This work seeks to explain this paradox. We identify a certain property of circuits which facilitates eecient solution of ATPG-SAT instances arising from them. In addition, we provide both theoretical proofs and empirical evid...

UML (Unified Modeling Language) as a standard as a standard of specification of object systems should be a natural source of information relevant to the testing. However, the systems are usually very complex. Moreover, the UML models contain a lot of data which are difficult for formalization and require human assistance. This makes ATPG (Automatic Test Pattern Generatio) from UML very doubtful...

Automatic test pattern generation (ATPG) for sequential circuits remains one of the most compute-intensive tasks in the integrated circuit design process. Although numerous attempts have been made to speed the ATPG process via parallelization, these attempts have often proved disappointing when compared against the best available serial algorithms using metrics of resultant quality and performa...

This paper starts with a comprehensive survey on RTL ATPG. It then proposes a novel RTL ATPG model based on ”Gate Inherent Faults” (GIF). These GIF are extracted from each complex gate (adder, case-statement, etc.) of the RTL source code individually. They are related to the internal logic paths of a complex gate. They are not related to any net/signal in the RTL design. It is observed, that wh...

Industrial circuits contain, in addition to the binary logic elements n]and, n]or and n]xor gates, other logic elements such as three-state elements, busses and bidirectionals. Previous published work on automatic test pattern generation (ATPG) can not handle all of the above mentioned circuit elements, generates too large test sets, or generates test patterns which can cause circuit damage. A ...

By adding a few logic gates and one or two modeling flip-flops to the circuit under test (CUT), we create a detection or diagnostic automatic test pattern generation (ATPG) model of transition delay faults usable by a conventional single stuck-at fault test pattern generator. Given a transition delay fault pair, the diagnostic ATPG model can either find an exclusive test or prove the equivalenc...

This thesis presents four different techniques for improving the average-case performance of deterministic sequential circuit Automatic Test Patterns Generators (ATPG). Three techniques make use of information gathered during test generation to help identify more unjustifiable states with higher percentage of “don’t care” value. An approach for reducing the search space of the ATPG was introduc...

Timing-related defects are becoming increasingly important in nanometer technology designs. Small delay variations induced by crosstalk, process variations, powersupply noise, as well as resistive opens and shorts can potentially cause timing failures in a design, thereby leading to quality and reliability concerns. We present a testgrading technique to leverage the method of output deviations ...

Genetic algorithms have proven to be a viable solution to the NP-complete problem of test vector generation. However, the parameters used to control GA-based ATPG can greatly affect test set size, fault coverage, and CPU execution time. Knowing how a given set of parameters will affect each of these factors a priori allows for more efficient testing procedures. Over 1 million ATPG experiments w...