The branch predictor plays a crucial role in the achievement of effective performance in microprocessors with pipelined architectures. This paper analyzes performance of branch prediction unit for pipelined processors. A memory of 512 bytes is designed for storing instructions. A 32 byte memory is designed for branch target buffer (BTB). This memory is utilized for storing history of the branch...

Improving static branch prediction accuracy is an important problem with various interesting applications. First, several compiler optimizations such as code layout, scheduling, predication, etc. rely on accurate static branch prediction. Second, branches that are statically accurately predictable can be removed from the dynamic branch predictor thereby reducing aliasing. Third, for embedded mi...

The main aim of this work is to propose a new Two Level Adaptive Branch Prediction scheme, based on a new additional correlation information. We prove that branch's history is insufficient for a good branch correlation and as a consequence, for high prediction accuracy. Also, we investigate comparatively, through a trace driven simulation method, a classical branch prediction scheme called GAp,...

In this paper we discuss an alternative to the existing branch prediction algorithms, called pre-computed branch prediction. This method does not actually involve prediction, as the branch's outcome is calculated as soon as its last operand is known. We attempted to validate the claim that pre-computed branches give a higher rate of performance than the existing branch prediction methods, by im...

Branch prediction is one of the main hurdles in the roadmap towards deeper pipelines and higher clock frequencies. This work presents a new approach to enhancing current branch predictors: Selective Branch Prediction Reversal. The rationale behind this proposal is the fact that many branch mispredictions can be avoided if branch prediction is selectively reversed. We present a Branch Prediction...

While delayed branch mechanisms were popular with the designers of RISC processors, most superscalar processors deploy dynamic branch prediction to minimise run-time branch penalties. We propose a generalised branch delay mechanism that is more suited to superscalar processors. We then quantitatively compare the performance of our delayed branch mechanism with run-time branch prediction, in the...

Ubiquitous systems use context information to adapt appliance behavior to human needs. Even more convenience is reached if the appliance foresees the user’s desires and acts proactively. This paper focuses on context prediction based on previous behavior patterns. The proposed prediction algorithms originate in branch prediction techniques of current high-performance microprocessors which are t...

Intel’s P6 processor (see 090202.PDF) is the first to use a two-level branch-prediction algorithm to improve accuracy. This algorithm, first published by Tse-Yu Yeh and Yale Patt, has the potential to push accuracy well beyond the 90% level achieved by the best processors today. As future processors look to improve performance by increasing the issue rate and/or extending the pipeline depth, th...

The majority of currently available dynamic branch predictors base their prediction accuracy on the previous k branch outcomes. Such predictors sustain high prediction accuracy but they do not consider the impact of unbiased branches, which are difficult-to-predict. In this paper, we evaluate the impact of unbiased branches in terms of prediction accuracy on a range of branch difference predict...

Modern micro-architectures employ superscalar techniques to enhance system performance. Since the superscalar microprocessors must fetch at least one instruction cache line at a time to support high issue rate and large amount speculative executions. There are cases that multiple branches are often encountered in one cycle. And in practical implementation this would cause serious problem while ...