The generation of significant power droop (PD) during at-speed test performed by Logic BIST is a serious concern for modern ICs. In fact, the PD originated during test may delay signal transitions of the circuit under test (CUT): an effect that may be erroneously recognized as delay faults, with consequent erroneous generation of test fails, and increase in yield loss. In this paper, we propose...

We present a new low-power BIST (built-in-self-test) for sequential circuits. State correlation analysis is first performed on the flip-flop values in the relaxed, compacted sequence for the undetected faults to extract spatial correlations among the flip-flops. The extracted spatial correlation matrix not only provides additional metrics through which the scan order may be altered, but also al...

One of the tenets of equilibrium asset pricing models is that expected return of an asset is positively related to its risk (price variability of the asset). In other words, it is expected that assets with higher expected returns are also the ones with higher risk, or assets with lower risk are the ones with lower expected returns. The logic behind this idea is actually is simple and intuitive:...

The main aim of this paper is to design and implement efficient UART and test the UART with built in self testing technique . A new Test pattern generator is simulated and used in BIST architecture in order to reduce power dissipation. As we know that power dissipation is more during the test mode than in normal mode hence In this project the pattern generator used is the low power pattern gene...

The increasing growth of sub-micron technology has resulted in the difficulty of testing. Design and test engineers have left no choice but to accept new responsibilities that had been performed by group of technicians in the previous years. Design engineers who do not design systems with full testability had increased the possibility of product failures and missed market opportunities. BIST is...

We present a methodology to detect and measure the signal overshoots occurring on the interconnects of high-speed system-on-chips. Overshoots are known to inject hot-carriers into the gate oxide which cause permanent degradation of MOSFET transistors’ performance over time. We propose a built-in chip mechanism to detect overshoots, collect the occurrence information and scan them out efficientl...

This technical report contains the text of Nur Touba's thesis "Synthesis Techniques for Pseudo-Random Built-In Self-Test." The thesis appendices have appeared as CRC Technical Reports, and are not included here.

As we approach 100nm technology the interconnect issues are becoming one of the main concerns in the testing of gigahertz system-onchips. Voltage distortion (noise) and delay violations (skew) contribute to the signal integrity loss and ultimately functional error, performance degradation and reliability problems. In this paper, we first define a model for integrity faults on the high-speed int...