In a conventional grid connected photovoltaic system employing centralized inverter with long strings connected across dc-link, the performance of the plant in terms of power generation and efficiency is not optimal especially during partial shading and/or panel mismatch conditions. To improve the power yield during such conditions, a splitmultistring configuration employing 3Level Neutral Poin...

A 15-b l-Msample/s digitally self-calibrated pipeline analog-to-digital converter (ADC) is presented. A radix 1.93, 1 b per stage design is employed. The digital self-calibration accounts for capacitor mismatch, comparator offset, charge injection, finite op-amp gain, and capacitor nonlinearity contributing to DNL. A THD of –90 dB was measured with a 9.8756-kHz sine-wave input. The DNL was meas...

This paper describes a 14-bit 2OMSPS switched-capacitor Stage Stae21t Sage N pipelined ADC that employs digital background calibration to N correct capacitor mismatch. The calibration concept is amenable to Digital correction Logic l_ Y implementation in SOC because it is digital in nature. The Digitalout calibration concept is demonstrated offline though in principle it can be included on-chip...

In this paper, a robust cyclic ADC architecture with βencoder is proposed and circuit scheme using switched-capacitor (SC) circuit is introduced. Different from the conventional binary ADC, the redundancy of proposed cyclic ADC outputs β-expansion code and has an advantage of error correction. This feature makes ADC robust against the offset of comparator capacitor mismatch and finite DC gain o...

A 6-bit, 7 mW, 700 MS/s subranging ADC using Capacitive DAC (CDAC) and gate-weighted interpolation fabricated in 90 nm CMOS technology is demonstrated. CDACs are used as a reference selection circuit instead of resistive DACs (RDAC) for reducing settling time and power dissipation. A gate-weighted interpolation scheme is also incorporated to the comparators, to reduce the circuit components, po...

This paper proposes a very simple method of eliminating the gain and offset errors caused by mismatches of elements, such as capacitors, for a high-speed CMOS pipelined ADC with a 1.5-bit architecture. The gain and offset errors in a bit-block due to capacitor mismatch are analog-to-digital (A-D) converted without correcting errors, but by exchanging capacitors at every clock. The obtained resu...

A radix-based digital self-calibration technique for multistage analog-to-digital converter(ADC) is presented. This technique can correct errors due to capacitor mismatch and finite opamp gain. The equivalent radix of each stage is extracted by measuring the discontinuity on the ADC transfer curve and iteratively adjusting the equivalent radix to minimize this discontinuity. A much more accurat...

This paper presents a 12-bit 100-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) for low-power wireless and imaging systems. A split-capacitor digital-to-analog (CDAC) structure is adopted reducing the core area improving sampling speed. The linearity of CDAC calibrated by programming least-significant-bits (LSBs) dummy capacitor. unit capacitor in ar...

A reconfiguration technique using a switched-capacitor (SC)-based voltage equalizer differential power processing (DPP) concept is proposed in this paper for photovoltaic (PV) systems at cell/subpanel/panel-level. The active diffusion charge redistribution (ADCR) architecture increases the energy yield during mismatch and adds boosting capability to PV system under no by connected available cel...