Computer-aided design (CAD) tools are frequently employed to verify the design objectives before the fabrication of an integrated circuit. An important circuit parameter that requires accurate characterization is the power consumption due to the strict constraints on the acceptable power envelope of integrated systems. Circuit simulators typically provide built-in functions to measure the power...

During the last decade, the complexity and size of circuits have been rapidly increasing, placing a stressing demand on industry for faster and more efficient CAD tools for VLSI circuit layout. One major problem is the computational requirements for optimizing the place and route operations of a VLSI circuit. Thus, this paper investigates the feasibility of using reconfigurable computing platfo...

The worldwide diffusion of wireless telecommunication systems opened new perspectives for microwave technologies. High-volume microwave monolithic integrated circuit (MMIC) production became a reality, revolutionizing the approach to microwave-circuit design. Nowadays, this is based on the intensive use of accurate simulation and computer-aided-design (CAD) tools. While scattering parameter mea...

We motivate and describe an analog evolvable hardware design platform named GRACE (i.e. Generative Robust Analog Circuit Exploration). GRACE combines coarse-grained, topological circuit search with intrinsic testing on a Commercial Off-The-Shelf (COTS) field programmable device, the Anadigm AN221E04. It is suited for adaptive, fault tolerant system design as well as CAD flow applications.

This paper surveys recent publications on the new class of layered circuit integration techniques termed 3D integration. We describe both the potential benefits and major pitfalls of 3D integration. Several competing layering approaches are described and compared. We also forecast the impact that a move to 3D integration would have on CAD tools and circuit design flows.

CAD plays a fundamental role in both top-down and bottom-up system fabrication. This paper presents a bottom-up circuit patterning process based on DNA selfassembly in terms of the design tool requirements and the new opportunities self-assembly creates for circuit designers. The paper also connects recent demonstrations of addressable selfassembly to applications in computer architecture and s...

PARTIAL CAD I: THE LIFTING PHASE (EXTENDED TECHNICAL REPORT) GRANT OLNEY PASSMORE AND PAUL B. JACKSON LFCS, Edinburgh and Clare Hall, Cambridge, 10 Crichton Street, Edinburgh EH8 9AB, UK e-mail address: [email protected] LFCS, Edinburgh, 10 Crichton Street, Edinburgh EH8 9AB, UK e-mail address: [email protected] Abstract. Though decidable, the theory of real closed fields (RCF) is fund...

Modeling and simulation of lithography and topography for processes and inspection in fabricating integrated circuits are the subject of this monograph. The introduction begins by establishing an appreciation for the revolutionary impact of the planar IC process, its growth in complexity, and the pace at which technologists are being asked to develop future generations. The role of modeling and...