This paper describes a clock and data recovery (CDR) circuit that supports dual data rates of 2.7Gbps and 1.62Gbps for DisplayPort standard. The proposed CDR has a dual mode voltage-controlled oscillator (VCO) that changes the operating frequency with a “Mode” switch control. The chip has been implemented using 0.18μm CMOS process. Measured results show the circuit exhibits peak-to-peak jitters...

Abstract The RD53B chip for HL-LHC upgrades of ATLAS and CMS pixel detectors needs to provide reliable operation in a radiation hostile environment with inevitable Single Event Effects (SEE). To answer the challenge, substantial efforts are made protect evaluate critical parts digital logic characterize on-chip Clock Data Recovery (CDR) circuit. SEE sensitivity is evaluated by testing both heav...

Version 1c, 4 May 2010 High speed serial data links are expected to transmit data at very high rates with very high fidelity. Today speeds approaching 10 Gb/s are becoming common with 40 Gb/s on the horizon. Typically, a maximum bit-error rate (BER) of 10–12-10–15 is required. Verifying such a small BER with direct simulation is quite impractical. Instead, a procedure is presented that separate...

Clock and data recovery (CDR) circuits are key electronic components in future optical broadband communication systems. In this paper, we present a 40-Gb/s integrated CDR circuit applying a phase-locked loop technique. The IC has been fabricated in a 50-GHz f T self-aligned double-polysilicon bipolar technology using only production-like process steps. The achieved data rate is a record value f...

A Bang-Bang Clock-Data Recovery (CDR) for 10 Gb/s optical transmission systems is presented. A direct modulated architecture is used for the design. Its loop characteristics can be derived using an analogy to 61 theory. The circuit was produced and measured in a commercial 0.25μm BiCMOS technology with a transition frequency fT=70 GHz.

This paper presents an inductive coupling interface using a relay transmission scheme and a low-skew 3D clock distribution network synchronized with an external reference clock source for 3D chip stacking. A relayed transmission scheme using one coil is proposed to reduce the number of coils in a data link. Coupled resonation is utilized for clock and data recovery (CDR) for the first time in t...

This article describes some techniques for implementing low-power clock and data recovery (CDR) circuits based on gated-oscillator (GO) topology for short distance applications. Here, the main tradeoffs in design of a high performance and power-efficient GO CDR are studied and based on that a top-down design methodology is introduced such that the jitter tolerance (JTOL) and frequency tolerance...

In this paper, it is proposed a jitter analysis methodology, targeting on the optimization of phase interpolator (PI) based clock and data recovery circuit (CDR). The methodology applied for optimized design an 8-bit dual-loop CDR, designed with CMOS TSMC 65 nm process node. CDR extended, in terms resolution, version, novel PI topology work. loop has minimum frequency offset tracking ability eq...

In this paper, an energy efficient digital baseband circuit for piezoelectric (PE) harvester powered batteryless remote control system is presented. Pulse mode PE harvester, which provides short duration of energy, is adopted to replace conventional chemical battery in wireless remote controller. The transmitter digital baseband repeats the control command transmission once the digital circuit ...