نتایج جستجو برای: clocking zones
تعداد نتایج: 46802 فیلتر نتایج به سال:
In this paper, we discuss arithmetic structures based on quantum cellular automata (QCA). By taking advantage of the unique capabilities of QCA we are able to design interesting computational architectures. We describe important design considerations and show how addition and multiplication circuits can be implemented using QCADesigner, a QCA design tool which has been developed in our laborato...
This paper introduces a distributed approach to interleaving paralleled power converter cells. Unlike conventional methods, the distributed approach requires no centralized control, automatically accommodates varying numbers of converter cells, and is highly tolerant of subsystem failures. A general methodology for achieving distributed interleaving is proposed, along with a specific implementa...
A detailed numerical simulation of the free charge trsnrfer in overlapped gate charge-coupled devices (CCD) is presented. The transport dynamics are analyzed in terms of thermal diffusion, self-induced fields, and fringing fields under all the relevant electrodes and the interelectrode regions with time-varying gate potentials. The results of the charge trmwfer with clifferent clocking schemes ...
A critical problem in building long systolic arrays lies in efficient and reliable synchronization. We address this problem in the context of synchronous systems by introducing probabilistic models for two alternative clock distribution schemes: tree and straight-line clocking. We present analytic bounds for the Probability of Failure and the Mean Time to Failure, and examine the trade-offs bet...
Clocking considerations and clocked storage elements for System on a Chip are discussed. Various ways of SOC clocking are addressed. We discuss issues of particular importance for SOC such as “time borrowing” and absorption of clock uncertainties. Clock power savings techniques suitable for SOC are described.
An interface for MEMS gyroscope is implemented in 0.18μm HVCMOS technology, and achieves a low noise floor of 1m°/sec/ Hz over 200Hz BW. Electromechanical forcefeedback and self-clocking scheme based on gyro resonance are implemented. The interface includes on-chip reference generation, decimation, and temperature compensation. Keywords-gyroscopes; Sigma delta modulation; Force feedback; Self-c...
Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor family. The latency of AQFP circuits relatively long compared to that other families and thus such require low-latency clocking schemes. In a previous study, we proposed scheme called delay-line clocking, in which the for each operation determined by propagation delay excitation current, demonstrated simple buf...
ElectroMagnetic Interferences (EMI) are emerging problems in today’s high speed circuits. There are several examples that these interferences affected the circuits and systems. This work tries to reduce the abovementioned problems in synchronous systems by modifying the clock signal such that it produces less interferers. In this thesis first EMI and its sources and related definitions are stud...
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