| We present formula of propagation delay for static CMOS logic gates considering short-circuit current and current owing through gate capacitance and using the n-th power law MOSFET model which considers velocity saturation e ects. The short circuit current is represented by a piece-wise linear function, which enables detailed analysis of the transient behavior of a CMOS inverter. We found tha...

In this paper, a test circuit is proposed for detecting open leads of CMOS logic ICs by means of supply current of a circuit under test. The circuit consists of a supply current measurement circuit and a test stimulus generator. The test stimulus generator is designed so that high speed test can be realized. Also, it is shown by some experiments that open leads of CMOS ICs will be detected at t...

Application specific full custom design integrated circuit is a methodology for making a logic cell, circuit or layout specification. Full custom design circuit is the part of Application specific integrated circuit. A gate array or uncommitted logic array as an approach to the design and manufacture of application specific integrated circuit. It requires custom chip fabrication using a complet...

Various adiabatic logic circuits can be used for minimizing the power dissipation. To enhance the functionality and performance of circuit two adiabatic logic families PFAL and ECRL have been used and compared with CMOS logic circuit design. In this paper, A MASTER-SLAVE D flip-flop is proposed by the use of SPICE simulation on 90nm technology files. The simulation result shows that PFAL is a b...

The authors report a 0.7V Manchester carry look-ahead circuit using partially depleted (PD) SOI CMOS dynamic threshold (DTMOS) techniques for low-voltage CMOS VLSI systems. Using an asymmetrical dynamic threshold pass-transistor technique with the PD-SOI DTMOS dynamic logic circuit, this 0.7V PD-SOI DTMOS Manchester carry look-ahead circuit has an improvement of 30% in propagation delay time co...

New true-single-phase-clocking (TSPC) BiCMOS/ BiNMOS/BiPMOS dynamic logic circuits and BiCMOS/BiNMOS dynamic latch logic circuits for high-speed dynamic pipelined system applications are proposed and analyzed. In the proposed circuits, the bootstrapping technique is utilized to achieve fast near-full-swing operation. The circuit performance of the proposed new dynamic logic circuits and dynamic...

Abstract The paper presents a split-level sinusoidal power supply clock generator circuit for Two-Phase Adiabatic Static CMOS Logic circuit (2PASCL). The driving of adiabatic logic requires adiabatic controlled sources of voltage. We study the clock voltage generator circuit using SPICE simulation and investigate the most suitable scheme and highest energy efficiency for the energy recovery pow...

In this paper, the design of a low power and high performance dynamic circuit using a new CMOS domino logic family called feedthrough logic is presented. The need for faster circuits with low power dissipation has made it common practice to use feedthrough logic. The proposed circuit for low power improves dynamic power consumption as compared to the existing feedthrough logic and improves its ...

An adiabatic logic is a technique to design low power digital VLSI’s. This paper describes the design and VLSI implementation of a multiplier using a two phase drive adiabatic dynamic CMOS logic (2PADCL) circuit. Circuit operation and performance have been evaluated using a 4×4-bit 2PADCL multiplier fabricated in a 1.2 μm CMOS process. The experimental results show that the multiplier was opera...

Dynamic logic style is used in high performance circuit designs because of its faster speed and lesser transistor requirement as compared to static CMOS logic style. Dynamic logic has inherent disadvantages like less noise immunity and high power consumption. In this paper we have proposed a novel circuit technique for implementing dynamic gate. The proposed circuit has very less power dissipat...