The performance of integrated circuits has been improving exponentially for more than thirty years. During the next decade, the industry must overcome several technological challenges to sustain this remarkable pace of improvement. Challenges in lithography, transistor scaling, interconnections, circuit families, computer memory, and circuit design are outlined. Possible solutions are briefly d...

In recent years, the mobile communication market represented by the mobile telephone has been showing remarkable growth. This market has been making tough demands for semiconductor integrated circuits, which are mounted components, to consume less power, have higher integration, have multi-function capability, and be faster. We at Oki have been working on developing complete depletion type SOI ...

Physical limitations of Complementary Metal-Oxide-Semiconductors (CMOS) technology at nanoscale and high cost of lithography have provided the platform for creating Quantum-dot Cellular Automata (QCA)-based hardware. The QCA is a new technology that promises smaller, cheaper and faster electronic circuits, and has been regarded as an effective solution for scalability problems in CMOS technolog...

Domino logic is a CMOS-based evolution of the dynamic logic techniques. It allows a rail-to-rail logic swing. It was developed to speed up circuits. In integrated circuit design, dynamic logic (or sometimes clocked logic) is a design methodology in combinatorial logic circuits, particularly those implemented in MOS technology. This work is oriented towards implementing the domino logic circuits...

This paper describes the parameter and characteristic analysis of Low power and High speed CMOS Logic Circuits in 90nm Technology. The proposed CMOS logic circuits consists only logic gates. CMOS circuit is fabricated in 0.12μm and 90nm CMOS technology. The supply voltage is 1.20V. The temperature was 27oC. We observed Inverter (NOT gate) properties MOS, Capacitance, Resistance, Inductance and ...

CMOS image sensors are a second-generation solid­ state imaging technology. CMOS active pixel sensors have performance competitive with CCD technology, and offer advantages in on-chip functionality, system power reduction, cost and miniaturization. CMOS VLSI circuits for imaging and readout, and on-chip integration of ADC and smart functions will be addressed.

CMOS active pixel sensor (APS) technology has been developed as a potential replacement for charge-coupled devices (CCDs) for solid-state imaging. The CMOS APS has several advantages over CCDs for camera systems including much lower camera power, smaller camera size, lower camera cost, and on-chip functionality. This paper describes the CMOS APS technology.

A 4MHz-10GHz, 10ps/dec dynamic comparator with using negative resistance and CMOS input differential pair is proposed and designed in IBM 130nm CMOS process technology. In this design, we effort that taking maximum sampling frequency from CMOS technology and the proposed comparator consumes 110nw-146μW at 1.5V supply.

This paper presents the design and performance comparison of a two stage operational amplifier topology using CMOS and BiCMOS technology. This conventional op amp circuit was designed by using RF model of BSIM3V3 in 0.6 μm CMOS technology and 0.35 μm BiCMOS technology. Both the op amp circuits were designed and simulated, analyzed and performance parameters are compared. The performance paramet...