A modif ied ring oscillator presented in this paper. The voltage control oscillator is designed and simulated in 50nm CMOS technology. The frequency of oscillation of the VCO is 2.6GHz with 0.064 mW power dissipation and the center drain current of 64uA is us ed. Tuning range is of 72% and the jitter is of 39.8pS. Index Terms Voltage Controlled Oscillator (VCO), power dissipation, jitter, tunin...

Today quadrature signals for IQ demodulation are provided through RC polyphase networks, quadrature oscillators or double frequency VCOs. This paper presents a new method for generating quadrature signals in integrated circuits using only inductors and capacitors. This LC quadrature generation method enables significantly reduced noise and power consumption.

Realization of a novel single-resistance-controlled oscillator, employing an active element and all grounded passive elements, is the purpose of this manuscript. With requirements for completing the design being only a single Voltage Differencing Current Conveyor and four grounded passive components, it is also a preferable choice for integrated circuit implementation. The designed circuit has ...

in this paper, solution of nonlinear optimal control problems and the controlled duffing oscillator, as a special class of optimal control problems, are considered and an efficient algorithm is proposed. this algorithm is based on state parametrization as a polynomial with unknown coefficients. by this method, the control and state variables can be approximated as a function of time. also, the ...

This paper presents a Low power consumption & Low phase Noise Voltage Controlled Ring Oscillator (VCRO) operated at 2.45 GHz. Frequency implemented in 0.18 μm complementary metal-oxide semiconductor (CMOS) technology with the unique differential delay cell. The Voltage Controlled Ring Oscillator is design in Tanner Tool Version 13 environment. Power Consumption should be reduced to improve the ...

Here, two new designs of CMOS digitally controlled oscillators (DCO) for low power application have been proposed. First design has been implemented with one driving strength controlled delay cell and with two NAND gates used as inverters. The second design with one delay cell and by two NOR gates is presented. The proposed circuits have been simulated in spice with 0.35 μm (micrometer) technol...

This paper presents a new consistent analysis of self-oscillating active inductors together with a complete design example of a 90 nm CMOS current controlled oscillator (CCO) for ISM applications. Using the proposed passive compensation method in place of a standard negative impedance converter, typical performance of active inductor oscillator is achieved with reduced static power consumption....

This paper presents a ring oscillator with the function of the oscillation controlled for wireless sensor systems (WSSs). The proposed oscillator consists of a NAND gate, 4 inverters, and 1-, 3-, 9-times buffer stage. Operation of it is controlled by the NAND gate. The oscillator can reduce the power loss because the oscillator is oscillated during only high level input. The proposed oscillator...

This thesis describes the circuit level design of a 900MHz EA ring oscillator based phase-locked loop using 0.35um technology. Multiple phase noise theories are considered giving insight into low phase-noise voltage controlled oscillator design. The circuit utilizes a fully symmetric differential voltage controlled oscillator with cascode current starved inverters to reduces current noise. A co...