A set of conditions is presented to enhance the evolvability of an arti cial core memory programming system. A digital protein (CPU) composed of a sequence of digital amino acids (instructions) is considered, and a set of implementation criteria is given to maximize the functionality and evolvability of proteins. Next, for a case study, we present the basic design of an ALife system named SeMar...

A compiler translates a program written in a high-level programming language into machine code. In addition to performing the translation, the compiler applies many optimizations to the generated code to improve its performance. Since nearly all contemporary programs (both applications and systems) are written in high-level languages, the compiler plays an important role in determining performa...

A swap instruction, which exchanges a value in memory with a value of a register, is available on many architectures. The primary application of a swap instruction has been for process synchronization. In this paper we show that a swap instruction can often be used to coalesce loads and stores in a variety of applications. We describe the analysis necessary to detect opportunities to exploit a ...

A filter cache is proposed at a higher level than the L1 (main) cache in the memory hierarchy and is much smaller. The typical size of filter cache is of the order of 512 Bytes. Prediction algorithms popularly based upon the Next Fetch Prediction Table (NFPT) helps making the choice between the filter cache and the main cache. In this paper we introduce a new prediction mechanism for predicting...

The method used to save and restore the values of registers across function calls can affect performance and influence the design of specific instructions. This paper describes the results of an experiment that empirically evaluated six different schemes for saving and restoring registers on CISC machines. The methods do not require special hardware or interprocedural analysis to be performed. ...

İşlemcinin verimliliğini arttırabilmek amacıyla bu çalışmada, Döner Çekirdek Algoritması, Genetik Algoritma ile geliştirilmiştir. Kuyrukta bekleyen işlemler ve onlara ait parametrelere uygun kuantum süresi seçilerek optimum değerlerin bulunması hedeflenmiştir.

Designing high-performance low-energy register files is of critical importance to the continuation of current performance advances in wide-issue and deeply pipelined superscalar microprocessors. In this paper, we propose a new microarchitecture, the asymmetrically banked value-aware register file (AB-VARF), to exploit the prevailing narrow-width register values for low-latency and energy-effici...

* Oguz Ergin is currently with Intel Labs Barcelona, Spain. Abstract A significant fraction of the result values in today's superscalar microprocessors are delivered to their consumers via forwarding and are never read out from the destination registers. Such transient values are kept in the register file solely for the purpose of recovering the processor state on interrupts or exceptions. In t...

The VAULT project is concerned with the design of a ‘multi-processor on a chip’ aimed specifically at multi-threaded Java implementation. It has wide ranging aims that require research in a variety of hardware and software areas. The project is still in its early stages and most of the work is still to do. This paper provides an overview of the project as envisaged currently and then examines s...

In this study, we pursue two main innovations. First, evaluate the predictive value of climate policy uncertainty (CPU) for oil market volatility. Second, demonstrate how an investor can exploit information contents CPU to gain higher returns. We find that increased values heighten crude risk, while forecast gains are achieved in a model accommodates CPU. further show observing offers portfolio...