A D flip-flop circuit that works well with long rise and fall times of the clock is characterized. This property is important when we would like to, e.g., relax the constraints on the clock distribution network or reduce the amount of noise generated in a mixed-signal circuit. Since the use of the D flip-flop allows small clock driver circuits, the amount of simultaneous switching noise can be ...

This article explains a new implementation of efficient D-Flip-Flop (DFF) using Gate-Diffusion-Input (GDI) technique, PowerPC, DSTC, and HLFF. This DFF design allows reducing power-delay product and area of the circuit, while maintaining low complexity of logic design. Performance comparison with other DFF design techniques is presented, with respect to gate area, number of devices, delay and p...

This paper enumerates low power, high speed design of D flip-flop. It presents various techniques to minimize subthershold leakage power as well as the power consumption of the

In this paper, a novel low power pulsed flip-flop (PFF) using self-controllable pass transistor logic is presented. The pulse generation logic comprising of two transistor AND gate is used in the critical path of the design for improved speed and reduced complexity. In the D to Q path inverter is removed and the transistor is replaced with pass transistor logic. The pass transistor is driven by...

This paper enumerates low power, high speed design of TSPC (True Single Phase Clocking) D flip-flop having less number of transistors. This technique allows circuit to achieve lowest power consumption with minimum transistor count. Design of low power device is now an essential field of research due to increase in demand of portable devices. In the circuit as the scaling increase the leakage po...

Flip Flops are critical timing elements in digital systems which has large impact on circuit speed and power consumption. The performance of flip flop is an important parameter to determine performance of whole synchronous circuit. In this paper, comparison of existing flip flops with different parameters is calculated. A new design a low power pulse triggered flip-flop (FF) has been proposed h...

We consider the problem of finding a local optimum for Max-Cut with FLIP-neighborhood, in which exactly one node changes the partition. Schäffer and Yannakakis (SICOMP, 1991) showed PLScompleteness of this problem on graphs with unbounded degree. On the other side, Poljak (SICOMP, 1995) showed that in cubic graphs every FLIP local search takes O(n) steps, where n is the number of nodes. Due to ...