A fast-lock and portable all-digital delay-locked loop (ADDLL) with 90◦ phase shift and tunable digitally-controlled phase shifter (DCPS) for DDR controller applications are presented. The ADDLL can achieve small phase-shift error in 1.3◦ at 400MHz and locking time of less than 13 clock cycles, making it very suitable for low-power DDR controller with power-down mode. The proposed DCPS provides...

A DLL(Delay Locked Loop) with DCC(Duty Cycle Correction) has become an essential block in high speed memory and digital circuits. An SMD(Synchronous Mirror Delay) structure is widely used both for skew reduction and for DCC. In this paper, an area-efficient DLL structure based on the merged dual SMD is proposed. The merged structure allows the forward delay array to be shared between the DLL an...

In this paper a new architecture for delay locked loops will be presented.  One of problems in phase-frequency detectors (PFD) is static phase offset or reset path delay. The proposed structure decreases the jitter resulted from PFD by switching two PFDs. In this new architecture, a conventional PFD is used before locking of DLL to decrease the amount of phase difference between input and outpu...

This paper presents the design of a clock and data recovery circuit having a high data rate of 9.95328 Gb/s by using delay locked loop with Switched Capacitor (SC) filter to improve the jitter transfer function and jitter tolerance as it has high Q and low center frequency. From the results it is seen that the besides the conventional DLL circuit , the circuit using SC filter of fc= 311.04 MHz ...

2 Digitizer 1GHz clock generation and control 5 2.1 Digitizer clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 Reference generation and coarse clock delay control . . . . . . . . . . . . . . . . . . . 6 2.3 Phase locked-loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 Digitizer clock fine delay control . . . . . . . . ...

Phase locked loops (PLL) and delay locked loops (DLL) play an important role in establishing coherent references (phase of carrier and symbol timing) in digital communication systems. Fully digital receiver including digital carrier synchronizer and symbol timing synchronizer fulfils the conditions for universal multi-mode communication receiver with option of symbol rate setting over several d...

A data driven multi-channel Time-to-Digital Converter (TDC) circuit with programmable resolution (25ps 800ps bin) has been implemented in a 0.25um CMOS technology. An on-chip PLL is used for clock multiplication up to 320MHz from an external 40MHz reference. A 32 element Delay Locked Loop (DLL) performs time interpolation down to 98ps. Finally, finer time interpolation is obtained using an on-c...

This paper examines the problems of symbol timing estimation and timing recovery for ultra wideband impulse radio signals. Two different approaches based on the maximum likelihood technique are investigated. The first approach is based on derivative matched filter and the second one takes advantage of the early-late technique. Furthermore, two non-coherent timing recovery circuits are proposed ...

A 3–8 GHz delay-locked loop (DLL) with cycle jitter calibration is presented. To lower the operation frequency of a voltage-controlled delay line (VCDL), this DLL adopts the dividers, an edge combiner, and the multiple VCDLs. A duty cycle correction circuit is presented to maintain the output duty cycle of 50%. This DLL has been fabricated in 90-nm CMOS process. The measured peak-to-peak jitter...