Chip-Scale Lidar by Behnam Behroozpour Baghmisheh Doctor of Philosophy Electrical Engineering and Computer Sciences University of California, Berkeley Professor Bernhard E. Boser, Chair The superiority of lidar compared to radio-frequency and ultrasonic solutions in terms of depth and lateral resolution has been known for decades. In recent years, both application pull such as 3D vision for rob...

We introduce a digital hologram generation of a real 3D object captured by a depth camera. The depth camera is employing a time multiplexed concept for color and depth image acquisition in a single chip sensor. The 3D information, point cloud, corresponding to the real scene, is extracted from taken image pairs, a gray texture and a depth map by a depth camera. The extracted point cloud is used...

In this paper, a new structure possessing the advantages of low-power consumption, less hardware and high-speed is proposed for fuzzy controller. The maximum output delay for general fuzzy logic controllers (FLC) is about 86 ns corresponding to 11.63 MFLIPS (fuzzy logic inference per second) while this amount of the delay in the designed fuzzy controller becomes 52ns that corresponds to 19.23 M...

Machining through turning was carried out in a lathe to study the chip formation of Multiphase Ferrite (F-B-M) microalloyed steel. Taguchi orthogonal array was employed to perform the machining. Continuous and discontinuous chips were formed for different cutting parameters like speed, feed and depth of cut. Optical and scanning electron microscope was employed to identify the chip morphology. ...

in this paper, a new structure possessing the advantages of low-power consumption, less hardware and high-speed is proposed for fuzzy controller. the maximum output delay for general fuzzy logic controllers (flc) is about 86 ns corresponding to 11.63 mflips (fuzzy logic inference per second) while this amount of the delay in the designed fuzzy controller becomes 52ns that corresponds to 19.23 m...

The distribution of a single global clock across a chip has become the major design bottleneck for high performance VLSI systems owing to the power dissipation, process variability and multicycle cross-chip signaling. A Network-on-Chip (NoC) architecture partitioned into several synchronous blocks has become a promising approach for attaining fine-grain power management at the system level. In ...

We propose an ultra low cost 2D-to-3D conversion system which generates depth maps using global scene depth gradient and texture-based local depth refinement. The depth gradient strength of global scene is generated by only analyzing the edge feature horizontally. Then the local pixel value, Y, Cb, and Cr component of the video content is used to refine the detail depth value. Combining the glo...

In the current context of miniaturization, micro-machining processes are in full expansion. One of them is micro-milling. Although micro-milling is based on the same principle as macro-milling, the phenomena of micro-cutting are not a simple scaling of macrocutting. A significant difference is the chip formation involving the phenomenon of minimum chip thickness. In micro-milling the depth of c...

We demonstrate and analyze a highly efficient on-chip 3D metal-insulator-metal (MIM) nanofocusing structure. Here, we show the in-depth theoretical design, analysis and discussion to provide a detailed picture of the highly efficient, on-chip nanofocusing process which is linearly tapered in 3D.