In this paper electrical characteristics of various kinds of multiple-gate silicon nanowire transistors (SNWT) with the channel length equal to 7 nm are compared. A fully ballistic quantum mechanical transport approach based on NEGF was employed to analyses electrical characteristics of rectangular and cylindrical silicon nanowire transistors as well as a Double gate MOS FET. A double gate, tri...

A hetero gate dielectric low band gap material DG Tunnel FET is presented here. The investigated device is almost free from short channel effects like DIBL and t V rolloff. Simulation of the device characteristics shows significant improvement over conventional double gate TFET when compared interms of on current, ambipolar current, roll-off, miller capacitance and, device delay time. Simulatio...

Abstract Multi-gate MOSFETs are considered for realizing ultra-low-power circuits due to their superior channel control capability and short effect (SCE) resistance. To achieve this goal, it is necessary establish a suitable compact device circuit model them. However, current research focuses more on single-material multi-gate MOSFET, there no report dual-material logic gates. In work, we devel...

We reported temperature-dependent narrow width effects on electrical characteristics of 28-nm CMOS transistors measured at temperature 77 K-300 K. At cryogenic temperatures, P-MOSFETs appear to have stronger temperature-induced threshold voltage ( $V_{\mathrm{ th...

In this paper, we have performed the scaling of asymmetric junctionless (JL) SOI nanowire (NW) FET at 10 nm gate length (LG). To study device electrical performance various DC metrics like SS, DIBL, ION/IOFF ratio are discussed. Even 5 nm, has good properties with subthreshold swing (SS) = ~64 mV/dec, drain induced barrier lowering (DIBL) ~45 mV/V, and switching (ION/IOFF) ~106 shows a higher l...

The global variability of ultra-thin body and buried oxide (UTBB) MOSFETs in subthreshold and off regimes of operation is analyzed. The variability of the off-state drain current, subthreshold slope, drain-induced barrier lowering (DIBL), gate leakage current, threshold voltage and their correlations are considered. Two threshold voltage extraction techniques were used. It is shown that the tra...