In high speed digital integrated circuits, interconnects delay can be significant and should be included for accurate analysis. Delay analysis for interconnect has been done widely by using moments of the impulse response, from the explicit Elmore delay (the first moment of the impulse response) expression, to moment matching methods which creates reduced order trans impedance and transfer func...

s previous work leading hiring discrimination investigations in the New York Attorney General's Civil Rights Bureau. The views expressed in this Article are the author's alone and do not reflect the views of the Bureau or the office. The author is grateful to Susan Plum and the Skadden Foundation for their unflagging support, to Maurice Emsellem, Noah Zatz, and Sharon Deitrich for helpful conve...

Past research on identity-based motivation theory (Oyserman, 2007; 2009) has shown that people given an interpretation of difficulty as importance outperform those given an interpretation of difficulty as impossibility or those given no interpretation on school tasks (Smith, Novin, Elmore, & Oyserman, under review). Paul, Smith, and Oyserman (2013) suggested that working memory may be a mechani...

Moments of the impulse response are widely used for interconnect delay analysis, from the explicit Elmore delay (the first moment of the impulse response) expression, to moment matching methods which creates reduced order trans-impedance and transfer function approximations. However, the Elmore delay is fast becoming ineffective for deep submicron technologies, and reduced order transfer functi...

School improvement policies converge on urban public schools in ways that paradoxically compromise school improvement—a challenge some have called a heightened state of policy incoherence (Fuhrman, 1993). These schools face a barrage of demands from various sources including federal and state governments, local school boards, unions, and community groups—these demands focus on numerous aspects ...

We describe an automated method (3D-map) for determining near-optimal decomposed generalized C-element (gC) implementations of extended burst-mode asynchronous controllers. Average-case optimization is performed so that frequent paths are accelerated, possibly at the expense of less frequent paths. The overall effect, as quantified using Elmore delay analysis, is a circuit that has near-optimal...

In high speed digital integrated circuits, interconnects delay can be significant and should be included for accurate analysis. Delay analysis for interconnect has been done widely by using moments of the impulse response, from the explicit Elmore delay (the first moment of the impulse response) expression, to moment matching methods which creates reduced order trans impedance and transfer func...

Conventional methods for optimal sizing of wires and transistors use linear RC circuit models and the Elmore delay as a measure of signal delay. If the RC circuit has a tree topology the sizing problem reduces to a convex optimization problem which can be solved using geometric programming. The tree topology restriction precludes the use of these methods in several sizing problems of signi cant...

In this paper, we study the wire sizing and wire spacing problem for post-layout performance optimization under Elmore delay model. Both ground capacitance and coupled capacitance in a wire are included in interconnect delay calculation. Combined with general ASIC design flow, we construct section constraint graph in each routing region and use the graph to guide segment sizing and spacing. By ...