A method is presented for deriving test suites with the guaranteed fault coverage for deterministic possibly partial Timed Finite State Machines (TFSMs). TFSMs have integer boundaries for time guards and the time reset operation at every transition; for TFSM implementations the upper bound on the number of states is known as well as the largest finite boundary and the smallest duration of time ...

The accumulator-based compaction (ABC) technique uses an accumulator to generate a composite fault signature for a circuit under test. The error coverage for this method has been previously analyzed using Markov chains. We describe an alternative technique for calculating the error coverage of ABC using the asymmetric error model. This technique relies on the central limit theorem of statistics...

The test can be developed at the functional level of the circuit. Such an approach allows developing the test at the early stages of the design process in parallel with other activities of this process. The main problem is the quality assessment of the functional test because the implementation of the circuit is not available yet. The paper presents the criteria of the quality assessment of the...

Time redundancy is a fault tolerance technique in which a task -either computation or communication -is performed multiple times on the same hardware. This technique is cheaper than other fault tolerance solutions that require some form of hardware redundancy, because it does not require replicated hardware. However, fault coverage may be lower with time redundancy as it only captures certain c...

The increasing use of hardware-software systems in costcritical and life-critical applications has led to heightened significance of design correctness of these systems. This paper presents a summary of research in hardware-software covalidation which involves the verification of design correctness using simulation-based techniques. This paper focuses on the test generation process for hardware...

This paper presents a fault model for interoperability testing of communication protocols that are modeled by communicating finite state machines, and proposes a technique that extends an initial interoperability test suite, which is given by another existing method, to be a test suite that can detect "almost all" interaction faults based on the fault model. We start with an interoperability te...

We present a technique that uses coverage measures in reliability estimation for fault tolerant programs, particularly N-version software. This technique exploits both coverage and time measures collected during testing phases for the individual program versions and the N-version software system for reliability prediction. The application of this technique on the single-version software was pre...

The analysis how the functional fault tests detect structural faults at gate-level shows that the stuck-at fault coverage is much higher than transition fault coverage. The aim of the paper is to discover the reasons of this phenomenon and to propose the techniques of functional delay test quality improvement. We suggest, by transformation of pin pair test into functional delay test, to use var...

A symbolic fault simulator is integrated in a Genetic Algorithm (GA) environment to perform Automatic Test Pattern Generation (ATPG) for synchronous sequential circuits. In a two phase algorithm test length and fault coverage as well are optimized. However, there are circuits with bad random testability properties, that are also hard to test using genetically optimized test patterns. Thus, dete...

March tests are widely used in the process of RAM testing. This family of tests is very efficient in the case of simple faults such as stuck-at or transition faults. In the case of a complex fault model—such as pattern sensitive faults—their efficiency is not sufficient. Therefore we have to use other techniques to increase fault coverage for complex faults. Multibackground memory testing is on...