changes in the physicochemical conditions of process unit, even under control, may lead to what are generically referred to as faults. the cognition of causes is very important, because the system can be diagnosed and fault tolerated. in this article, we discuss and propose an artificial neural network that can detect the incipient and gradual faults either individually or mutually. the main fe...

Fault simulation is a compute-intensive problem. Data parallel simulation on multiple processors is one method to reduce fault simulation time. In this paper , we discuss a novel technique to partition the fault set for data parallel fault simulation. When applied statically, the technique can scale well for up to eight processors. The fault set partitioning technique is simple, can itself be p...

Current paper presents an approach to emulate fault simulation of sequential circuits on FPGA. Fault simulation is an important subtask in test pattern generation and it is frequently used throughout the test generation process. In the paper, we explain the problems associated to fault emulation for sequential circuits. Two alternative approaches are described, which can be considered as trade-...

Fault simulation of a test set in an order different from the order of generation (e.g., reverse or random order fault simulation) is used as a fast and effective method to drop unnecessary tests from a test set in order to reduce its size. Recently in [1], we proposed an improvement to this type of fault simulation process that makes it even more effective in reducing the test set size. The pr...

A new technique is proposed to handle fault simulation at the architectural level. The technique bypasses the need for complete gate-level structure and e ciently uses the architectural information. Symbolic data representing groups of stuck-at faults, known as fault e ects, are propagated across the circuit with intelligent propagation prediction. Fault e ects may combine and form new groups i...

A new approach to parallel fault simulation for sequential circuits based on Binary Decision Diagrams (BDD) is proposed. The efficiency of BDDs for simulation is well known. However, traditional BDDs are not well-suited for fault simulation. Furthermore, up to now, they have not been used for parallel simulation. In the paper, a new class of BDDs is presented, called Structurally Synthesized BD...

-In this paper, a fault simulation method that utilizes behavioral pre-synthesis and gate level post-synthesis components models will be presented. In this method, an injected stuck at fault in a module will propagate through gates until it reaches the boundary of the module. Propagation of the fault in modules other than the one that it is initiated in will be done in behavioral models. This m...