In recent years, there has been an increasing demand for high-speed digital circuits at low power consumption. The use of dual edge-triggered flip-flops can help reduce the clock frequency to half of the single edge-triggered flip-flops while maintaining the same data throughput, this thereafter translates to better performance in terms of both power dissipation and speed. Pulsetriggered flip-f...

This paperreviews the three Conditional techniques for high performance flip-flops namely Conditional Precharge, Conditional Capture and Conditional Discharge. The classification of these techniques is based on how to prevent or reduce the unnecessary internal switching activities and reviewed in terms of Power and Delay.Comparison summary of flip-flops characteristics based on these techniques...

This paper reviews the three Conditional internal activity Techniques for high performance flip-flops namely Conditional Capture, Conditional Precharge and Conditional Discharge techniques. These techniques are reviewed in terms of power and delay and classified based on how to prevent or reduce the internal switching activity. Application of the Conditional techniques results in improvement of...

A partial scan selection strategy is proposed in which flip-flops are selected via newly proposed dynamic reachability and observability measures such that the remaining hard-to-detect faults are easily detected. This is done by taking advantage of the information available when a target fault is aborted by the test generator. A partial scan selection tool, IDROPS, has been developed which sele...

This paper presents adiabatic flip-flops based on CPAL (complementary pass-transistor adiabatic logic) circuits with energy-recycling output pad cells. The energy-recycling output pad cells for driving adiabatic chips include mainly bonding pads, ESD (electrostatic discharge) protection circuits, and two stage energy-recycling buffers. The adiabatic flip-flops and sequential circuits with energ...

Several dual-rail logic styles make use of single-rail flip-flops for storing intermediate states. We show that single mask bits, as applied by various side-channel resistant logic styles such as MDPL and iMDPL, are not sufficient to obfuscate the remaining leakage of single-rail flipflops. By applying simple models for the leakage of masked flip-flops, we design a new attack on circuits implem...