A CMOS memory-cell for dynamic storage of analog data and suitable for LVLP applications is proposed. Information is memorized as the gate-voltage of input-transistor of a gainboosting triode-transconductor. The enhanced output-resistance improves accuracy on reading out the sampled currents. Additionally, a four-quadrant multiplication between the input to regulation-amplifier of the transcond...

This paper proposes a current-controlled grounded memristor emulator circuit based on single four-quadrant analog multiplier, resistor and capacitor. The behavioral model of the proposed is analyzed, highlighting its characteristics. Experimental results are given to investigate ability for different operating frequencies they in accordance with theoretical analysis simulation results. By using...

A low-voltage, low-power four-quadrant analog multiplier with optimized current-efficiency is presented. Its core corresponds to a pseudodifferential cascode, gain-boosting triodetransconductor. According to a low-voltage 1.2μm CMOS n-well process, operand differential-amplitudes are 1.0Vpp and 0.32Vpp for a 1.3V-supply. Common-mode voltages are properly chosen to maximize current-efficiency to...

A four-quadrant analog multiplier with ultra-low supply voltage operation, rail-to-rail input swing and insensitive to different dc levels between the multiplied signals is presented. It based on Floating-Bulk technique, in which signal coupled bulk terminal of a PMOS transistor by means an capacitor. This allows operation eliminates level regardless offset them, maintaining linearity. Moreover...

CMOS technology, and the parasitic capacitances have been extracted from a layout which will be used for the integration of a multilayer perceptron with on-chip learning. The size of a complete 5bit storage cell is 1 2 0 ~ x 69pm ( 1 2 0 ~ x 1 9 ~ for the current sources). The weighted current sources are made, respectively, of 8-, 4-, 2-, I-unit transistors in parallel and 2unit transistors in...

This paper presents a four-quadrant multiplier based on square-law characteristic of floating gate MOSFET (FGMOS) in saturation region. The proposed circuit uses square-difference identity and the differential voltage squarer proposed by Gupta et al. to implement the multiplication function. The proposed multiplier employs eight FGMOS transistors and two resistors only. The FGMOS implementation...