Globally Asynchronous Locally Synchronous (GALS) Systems have provoked renewed interest over recent years as they have the potential to combine the benefits of asynchronous and synchronous design paradigms. It has been applied to ASICs, but not yet applied to FPGAs. In this paper we propose applying GALS techniques to FPGAs in order to overcome the limitation on timing imposed by slow routing.

GALS systems despite having well-known drawbacks such as non-mature design-flow, lack of testing methods and no well-established target application, may offer significant advantages like better EMI characteristics, power reduction and process variability mitigation. These advantages have been explored in detail with theoretical research and chip fabrication and measurements. In addition, a syst...

Globally asynchronous locally synchronous (GALS) clocking applied to a system-on-a-chip (SoC) results in a design in which each core is a synchronous block (SB) of logic with a locally generated clock. Inter-core communication is asynchronous and controlled by wrapper logic around the cores. The nondeterministic synchronization used by most GALS architectures makes chip-level silicon debug and ...

In this report, the possibilities of reducing EMI in GALS systems are investigated and presented. Based on the special software tool for EMI analysis, several different abstract models of GALS circuits have been designed in order to extract a realistic pausable clock behavior. Based on the clock behavior, we have been able to analyze using our tool the current profile of each modeled system, bo...

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In this paper a Globally Asynchronous Locally Synchronous (GALS) implementation of a complex digital system is discussed. The deployed asynchronous wrappers are based on a novel request-driven technique with embedded time-out function. Each GALS block is fitted with a local clock generator for flushing the internal pipeline stages when there are no incoming requests. This request-driven techniq...

Elliptic Curve Cryptography (ECC) represents the state-of-the-art of public-key cryptography. It is very computation intensive and hardware consuming for ASIC implementation. In this work, an ECC processor based on the Globally Asynchronous Locally Synchronous (GALS) design is presented. Attention has been paid on the resistances of GALS design against side-channel attacks (SCAs). The pausible ...

In Kahn process network (KPN), the processes (nodes) communicate by unbounded unidirectional FIFO channels (arcs), with the property of non-blocking writes and blocking reads on the channels. KPN provides a semantic model of computation, where a computation can be expressed as a set of asynchronously communicating processes. However, the unbounded FIFO based asynchrony is not realizable in prac...

The paper presents a programming language called DSystemJ, for dynamic distributed Globally Asynchronous Locally Synchronous systems (GALS), its formal model, formal syntax and semantics, its compilation and implementation. The language is aimed at dynamic distributed systems, which use socket based communication protocols for communicating between components. DSystemJ allows the creation and c...

This paper describes an implementation of a 2-dimensional DCT processor and shows that the Globally Asynchronous Locally Synchronous (GALS) approach is highly suitable for implementation of such processors. Primarily the GALS approach increases the design efficiency by using the divide-and-conquer approach. Simulation results on the port controller are presented.