The junctionless nanowire transistor is a promising alternative for a new generation of nanotransistors. In this letter the atomic force microscopy nanolithography with two wet etching processes was implemented to fabricate simple structures as double gate and single gate junctionless silicon nanowire transistor on low doped p-type silicon-on-insulator wafer. The etching process was developed a...

A three-dimensional (3D) fin-shaped field-effect transistor structure based on III-V metal-oxide-semiconductor field-effect transistor (MOSFET) fabrication has been demonstrated using a submicron GaAs fin as the high-mobility channel. The fin-shaped channel has a thickness-to-width ratio (TFin/WFin) equal to 1. The nano-stacked high-k Al2O3 dielectric was adopted as a gate insulator in forming ...

This paper proposes and demonstrates the extraction of MOSFET threshold voltage, source-drain resistance, gate field mobility reduction factor, and transistor gain factor from the measurement of the small-signal source-drain conductance of a transistor as a function of dc gate bias with zero dc drain bias. The theory is based on the analytical model that includes the effects of source-drain res...

A large amount of research is currently going on in the field of reversible logic, which have low heat dissipation, low power consumption, which is the main factor to apply reversible in digital VLSI circuit design. This paper introduces reversible gate named as 'Inventive0 gate'. The novel gate is synthesis the efficient adder modules with minimum garbage output and gate count. The I...

A neuron MOS transistor has a floating gate and multiple input gates which are capacitively coupling with the floating gate. Dramatic reduction in the number of transistors and interconnections was achieved by employing the neuron MOS in circuit designs. Since the neuron MOS gate electrode is electrically floating, it is not necessarily easy to calculate the floating gate potential using circui...

Physical faults include bridging faults, break (open) faults, transistor stuck-on and transistor stuck-off. Compared to traditional gate-level stuck-at faults, physical faults more closely represent realistic faults appearing at the gate level and transistor level. Analytical modelling for such faults, used for design and testability, is still a new and emerging area. Undetectable bridging faul...

It has been clear for a number of years that increasing transistor gate leakage with device scaling would ultimately necessitate an alternative to traditional SiON dielectrics with polysilicon gates. Material systems providing higher dielectric constants, and therefore allowing physically thicker dielectrics, have been the object of extensive research. Such high-k dielectrics, when combined wit...

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In this paper a method for choosing appropriate transistor topology for use with transistor sizing is presented. In combinatorial blocks of static CMOS circuits transistor sizing can be applied for delay balancing in order to guarantee synchronously arriving signal slopes at the input of logic gates. Since the delay of a logic gate depends directly on transistor sizes, the variation of channel-...

Oxide tunneling current in MOS transistors is fast becoming a non-negligible component of power consumption as gate oxides get thinner, and could become in the future the dominant leakage mechanism in sub-100nm CMOS circuits. In this paper, we present an analysis of static CMOS circuits from a gate-leakage point of view. We first consider the dependence of the gate current on various conditions...