In this work, an analytical model for estimation of width scalable architectural level leakage current of the 6T Static Random Access Memory (SRAM), considering its peripherals is proposed in 45nm technology. Based on the mode of operation of SRAM (read, write and idle phase), the width dependent leakage current is estimated at an early stage which reduces design time and aid to power managemen...

Dynamic logic is increasingly becoming a logic type of choice for designs requiring high speed and low area. Charge sharing is one of many problems that m a y cause failure in dynamic logic circuits due t o their low noise immunity . I n this paper, we address the charge sharing noise issue. Specifically, we develop an accurate but tractable model f o r analyzing charge sharing that avoids cost...

Artificial intelligence is integral part of a neural network is based on mathematical equations and artificial neurons. The focus here is the implementation of the Artificial Neural Network Architecture (ANN) with on chip learning in analog VLSI for pattern recognition. It is a maximum likelohood classifier which can be implemented using VLSI. Modified Hamming neural network architecture is pre...

A four-bit adder is simulated using HSPICE in two classic design methods: a ripple-carry adder (RCA) and a carry-look-ahead adder (CLA). All components of the adders are composed of PMOS, NMOS, and capacitors. The propagation delay and power dissipation were measured under different VDD values and different operating temperatures in HSPICE. A comparison of these two metrics were analyzed betwee...

In this paper, we present the design and experimental evaluation of an 8-bit adiabatic multiplier with built-in self-test (BIST) logic and an internal single-phase sinusoidal power-clock generatox Both the multiplier and the BIST have been designed in SCAL-D, a true single-phase adiabatic logic family. In HSPICE simulations with post-layout extracted parasitics, our design functions correctly a...

Crosstalk noises have been estimated both for RC and RLC interconnects, respectively, in deep submicron VLSI circuits. The 2π model approach has been employed. The victim line is considered as an RC or RLC line, and the aggressor line is placed near the victim line. The aggressor line is excited with a voltage pulse at the coupling location keeping the victim line quiet. Analytical expressions ...

Ternary logic has been proven to carry an information ratio 1.58 times that of binary and is capable reduce circuit interconnections complexity operations. However, the excessive transistor count ternary gates impeded their industry applications for decades. With modulation ferroelectric negative capacitance (NC) properties on channel potential, MOSFETs show many novel features including steep ...

This paper presents a novel HSPICE circuit model for designing and simulating a Single-Electron (SE) turnstile, as applicable at the nanometric feature sizes. The proposed SE model consists of two nearly similar parts whose operation is independent of each other; this disjoint feature permits the accurate and reliable modeling of the sequential transfer of electrons through the turnstile in the...

The synergistic effect of enhanced low dose rate sensitivity and single-event transients (SETs) in the bipolar dual operational amplifier LM158 is studied. test results show a significant reduction SET amplitude broadening waveform upon exposure to total ionizing radiation. These are much more prominent for (LDR) irradiation 0.01 rad(Si)/s than high 10 rad(Si)/s. greater gain degradation with L...

This report shows the leakage power and the access latency of a novel asymmetric SRAM cell [1] using HSPICE simulation under different scenarios for FPGA architecture. Then, it shows that we are able to take advantage of the features of asymmetric cells and achieve 2X leakage power reduction for LUT-based FPGA.