Logic synthesis is the process of automatically generating optimized logic level representation from a high-level description. With the rapid advances in integrated circuit technology and the resultant growth in design complexity, designers increasingly rely on logic synthesis to shorten the design time, while achieving performance objectives. This paper describes the IBM logic synthesis system...

   This paper presents a novel design of quaternary logic gates using graphene nanoribbon field effect transistors (GNRFETs). GNRFETs are the alternative devices for digital circuit design due to their superior carrier-transport properties and potential for large-scale processing. In addition, Multiple-valued logic (MVL) is a promising alternative to the conventional binary logic design. Sa...

The secret information, which is embedded in integrated circuit (IC) devices such as a smart card, has the risk of theft by reverse engineering (RE). The circuit design of IC can be stolen by the RE, and the counterfeit can be illegally fabricated. Therefore, the secure IC device requires the circuit architecture protected from the RE attacks. This paper proposes the diffusion programmable devi...

The high cost of IC design has made chip protection one of the first priorities of the semiconductor industry. Although there is a common impression that combinational circuits must be designed without any cycles, circuits with cycles can be combinational as well. Such cyclic circuits can be used to reliably lock ICs. Moreover, since memristor is compatible with CMOS structure, it is possible t...

We describe the use of hardware compilation techniques to provide a exible interfacing and computing platform for building self-validating (SEVA) sensors. SEVA technology has been developed at Ox-ford as a generic method of supplying a real-time guarantee on the quality of a physical measurement as well as the measurement itself. We describe the reconngurable hardware platforms that have been c...

Oneand two-dimensional iterative arrays of identical cells are becoming more important in the design of digital systems using large-scale integrated circuits because of the advantages that they provide in design, fabrication, and testing. Since arrays containing hundreds or thousands of gates on one chip are now considered possible, the task of finding procedures for the testing of such arrays ...

In a VHDL-based design flow for application specific integrated circuits, VITAL provides a uniform methodology for developing ASIC libraries for signoff simulation. The VITAL Standard includes specialized routines for describing behavior and timing of ASIC cells and integrates backannotation via Standard Delay Format (SDF). One of the key issues of the VITAL initiative was to accelerate simulat...

Exact power estimation, at logic level, is only possible if all the input correlations are taken into account. Recently, a probabilistic approach that uses a simple but powerful formalism for power estimation taking into account all the input correlations has been proposed. With this probabilistic approach it is possible to compute exactly the power dissipation of combinational modules using in...

This paper describes a self-timed integrated circuit for division and square-root extraction. First it concentrates on the development and the proof of a new mathematical algorithm. Then the design methodology and the architecture of a self-timed circuit implementing a simplified version of the algorithm is presented. The algorithm relies on two functional blocks, each simple enough to be fully...

We describe the embedding of the semantic notions and modal operators of a fir st-order temporal logic based on time intervals in a multivalued setting. Truth values will be realized as functions from time intervals to "ordinary" truth values like t and f . The main emphasis lies on the realization of the various modal operators contained in the temporal logic as operations on the functional tr...