This paper describes a scalable interconnect for distributed multimedia systems based on crossbar switches. The interconnect is scalable in that it can be used to interconnect a distributed system at different levels. At the lowest level, the interconnect replaces an I/O bus of a workstation in that a switch connects processors and memory with I/O devices. If a large number of devices have to b...

Interconnect tuning is an increasingly critical degree of freedom in the physical design of high-performance VLSI systems. By interconnect tuning, we refer to the selection of line thicknesses, widths and spacings in multi-layer interconnect to simultaneously optimize signal distribution, signal performance, signal integrity, and interconnect manufacturability and reliability. This is a key act...

In this paper, a novel first order self-balancing interconnect layout design is proposed for reducing plasmaprocess induced charging damage (P2ID) in modern CMOS processes. According to the mechanism of P2ID, dense interconnect lines collect positive charges due to electron shading (ES) effect [1] while sparse interconnect lines collect negative charges due to extended electron shading effect (...

I examine interconnection decisions of horizontally differentiated firms. I find that previous results that firms do not interconnect enough, based on the finding that consumers always benefit from interconnection, are only half right. In a Hotelling, as opposed to a Cournot, model consumers may suffer from interconnection, and the firms may interconnect when it is not socially optimal (interco...

This work presents methods for interconnect optimization while performing register optimization and placement of registers in memory. It has been shown that the port assignment problem is similar to the register optimization problem that also considers interconnect optimization. The basic formulation of the register-interconnect optimization problem has been posed as that of finding a clique co...

We present a sensitivity study approach to evaluate the effects of interconnect variations on the performance of large, complicated circuits. The approach uses highly efficient designed experiments. The results from the study of a multiplier circuit are presented as an example. 1.0 Introduction TodayÆs submicron circuits require a sensitivity study of interconnect variation on circuit performan...

Each new semiconductor technology node brings smaller transistors and wires. Although this makes transistors faster, wires get slower. In nano-scale regime, the standard copper (Cu) interconnect will become a major hurdle for FPGA interconnect due to their high resistivity and electromigration. This paper presents the comprehensive evaluation of mixed CNT bundle interconnects and investigates t...