scaling challenges and limitations of conventional silicon transistors have led the designers to apply novel nano-technologies. one of the most promising and possible nano-technologies is cnt (carbon nanotube) based transistors. cnfet have emerged as the more practicable and promising alternative device compared to the other nanotechnologies.  this technology has higher efficiency compared to t...

A carry-select adder can be implemented by using single ripple carry adder and an add-one circuit [1] instead of using dual ripple-carry adders. This paper proposes a new add-one circuit using the first zero finding circuit and multiplexers to reduce the area and power with no speed penalty. For bit length n = 64, this new carry-select adder requires 38 percent fewer transistors than the dual r...

Adiabatic logic is used to minimize the energy loss during operation of the circuit. Using two-phase adiabatic static CMOS logic (2PASCL) the power consumption can be reduced. This paper compares the power consumption of Static Energy Recovery Full Adder(SERF) and the proposed full adder using two phase adiabatic static CMOS logic(2PASCL). The average power consumption of proposed full adder is...

full adder cell is often placed in the critical path of other circuits. therefore it plays an important role in determining the entire performance of digital system. moreover, portable electronic systems rely on battery and low-power design is another concern. in conclusion it is a vital task to design high-performance and low-power full adder cells. since delay opposes against power consumptio...

A new dynamic differential logic family, Short-Circuit Current Logic (SCL), is proposed for low-power high-performance applications. It achieves low-power consumption by using an aggressively reduced logic swing without requiring restoration circuitry. Using a 0.35μm CMOS technology and a nominal supply voltage of 3.3V, a SCL full-adder 8 carry ripple adder (CRA) is implemented. It offers an or...

Design and simulation of conventional CMOS full adder using 45nm technology at specified node has been presented here. This research work shows comparison about post layout simulations of designed low power CMOS full adder. It also explains about performance analysis of optimized low power CMOS full adder at different loads. This design has achieved 63. 11nW active power consumption with propag...

In this article presents the investigation of array multipliers using SPL and control input technique based adder cells. The proposed SPL based adder cell consumes low power, small silicon area and low delay compared to control input technique based adder cell. The proposed circuit is tested with 4 bit array multiplier in terms of power, delay for 45 and 180 nm technology nodes. The array multi...

This paper presents a comparative study of different redundant binary full adders (Plus-Plus-Minus (PPM) adder). These PPM adders are simulated to evaluate their performance in total power dissipation, speed and PDP. The performances of these circuits are based on 180nm process model at a supply voltage of 1.8V. We also proposed a new design for PPM adder using 13-transistors. The simulation re...

In this paper, a proposed 1-bit hybrid full adder design employing both transmission gate logic and complementary metal– oxide–semiconductor (CMOS) logic is reported. The design is implemented for 1-bit Ripple Carry Adder and then is extended for 64-bit Ripple Carry Adder. The circuit is implemented using Mentor Graphics tools 130nm technology. The performance parameters such as delay, area, to...

This paper presents a novel method of hardware reduced fast FIR filter structure for parallel data processing.In general, arithmetic operation modules such as adder and multiplier modules, consume much power, energy, and circuit area. The power consumed by the adder structure is also very significant while designing a low power filter. The proposed low power multipliers and low power adders are...