Memories are most important building blocks in many digital systems. As the Integrated Circuits requirements are growing, the test circuitry must grow as well. There is a need for more efficient test techniques with low power and high speed. Many Memory Built in Self-Test techniques have been proposed to test memories. Compared with combinational and sequential circuits memory testing utilizes ...

A fast low-power 1-bit full adder circuit suitable for nano-scale CMOS implementation is presented. Out of the three modules in a common full-adder circuit, we have replaced one with a new design, and optimized another one, all with the goal to reduce the static power consumption. The design has been simulated and evaluated using the 65 nm PTM models.

Precise fine-grained office occupancy detection can be exploited for energy savings in buildings. Based on such information one optimally regulate lighting and climatization based the actual presence absence of users. Conventional approaches are movement detection, which cheap easy to deploy, but imprecise offer coarse information. We propose a power monitoring system as source information.The ...

Designing systems for low power, or low power codesign, was not very much addressed as a whole by the current research. There has been considerable work on low power hardware, some on software power consumption and little on low power communication. This paper will present a motivation for addressing power consumption at system level together with an overview of the design methods for low power...