Memory cores (especially SRAM cores) used on a system chip usually come from a memory compiler. Commercial memory compilers have their limitation— a large memory may need to be implemented with multiple small memories, if generated by memory compilers. In this paper we introduce a testability-driven memory optimizer and wrapper generator that generates BISTed embedded memories by using a commer...

1. Preface This report presents a compressive study on designing memory BIST. The study covers motivation behind memory BIST, algorithm of different test patterns, surveys of current memory BIST architecture, and discussion of various implementation issues. It is my best intention that this report will serve as a knowledge base for future design in memory BIST. The remainder of this report is o...

Flash memories are a type of non-volatile memory based on floating-gate transistors. The use of commodity and embedded flash memories are growing rapidly as we enter the system-on-chip (SOC) era. Conventional tests for flash memories are usually ad hoc—the test procedure is developed for a specific design. We propose improved March-like algorithms (i.e., March FT) for both bit-oriented and word...

The increased circuit density in today’s integrated circuits demands for efficient and low cost testing as compared to the testing of logic with external test equipment. The Built-In Self Test (BIST) architecture provides the self-testing of logic circuit but is not at the positive extreme in delivering deterministic and limited test vectors and storage and compression of output test responses....

Knowing, that the threshold voltage of the EEPROM memory cells is a key parameter to determine the overall performance of the memory, a build in structure to extract this information is a very relevant choice to fast diagnose failure in the memory. Thus, the objective of this paper is to present a built in self-diagnosis of EEPROM memory cells, based on threshold voltage extraction. In order to...

With the advance of VLSI technology, the capacity and density of memories is rapidly growing. The yield improvement and testing issues have become the most critical challenges for memory manufacturing. Conventionally, redundancies are applied so that the faulty cells can be repairable. Redundancy analysis using external memory testers is becoming inefficient as the chip density continues to gro...

We describe an experiment that was designed to explore differences between active and passive travelers in a way-finding task. In this study, we examined the effect of active travel mode on spatial and visual memory for a built environment. After completing a way finding task in a university campus, we tested participant’s memory for the test route using sketch map, mirror-image discrimination,...

In a carefully structured study spanning several months, the authors visited numerous companies focused on Design For Test methodologies in SoC Test, Characterization, and Failure Analysis. In interviews with the leading engineers in these projects, the various DFT structures and test processes used were studied. The results of the study revealed a number of impediments to the adoption of these...