This paper describes three new march tests for multiport memories. A read (or write) port in such a memory consists of an n-bit address register, an n-to-2n-bit decoder (with column multiplexers for the column addresses) and drivers, and a K -bit data register. This approach gives comprehensive fault coverage for both array and multiport decoder coupling faults. It lends itself to a useful BIST...

In this paper a method to obtain harmonic transfer matrices (HTM) from simulated or measured values (signature & signature response) is presented. These matrices subserve a description of complex systems (e.g. RF front-ends) with real properties, which can’t be specified by simple analytic expressions. They afford to give statements about a systems parameter. That’s why HTM are suitable for Bui...

Many believe that in-field hardware faults are too rare in practice to justify the need for Logic Built-In Self-Test (LBIST) in a design. Until now, LBIST was primarily used in safety-critical applications. However, this may change soon. First, even if costly methods like burn-in are applied, it is no longer possible to get rid of all latent defects in devices at leadingedge technology. Second,...

In mixed-mode BIST, deterministic test patterns are generated with on-chip hardware to detect the random-pattern-resistant (r.p.r.) faults that are missed by the pseudo-random patterns. While previous work in mixed-mode BIST has focused on developing hardware schemes for more efficiently encoding a given set of deterministic patterns (generated by a conventional ATPG procedure), the approach ta...

On Compact Test Sets for Multiple Stuck-At Faults for Large Circuits p. 20 Identification of Feedback Bridging Faults with Oscillation p. 25 Delay Fault and Memory Test Defining SRAM Resistive Defects and Their Simulation Stimuli p. 33 Vector-Based Functional Fault Models for Delay Faults p. 41 Easily Path Delay Fault Testable Non-Restoring Cellular Array Dividers p. 47 March Tests for Word-Ori...

In this paper we present a microprocessor-based approach suitable for embedded flash memory testing in a System-on-achip (SOC) environment. The main novelty of the approach is the high flexibility, which guarantees easy exploitation of the same architecture to different memory cores. The proposed approach is compatible with the P1500 standard. A case study has been developed and demonstrates th...

We have developed an algorithm by which to enable conventional microprocessors to test their on-chip SRAM using their existing hardware and software resources. This test method utilizes a mixture of existing memory testing techniques, which cover all important memory faults. This i; achieved by writing a routine called BIST Program by which only uses the existing ROM and creates no additional h...

Memory cores (especially SRAM cores) used on a system chip usually come from a memory compiler. Commercial memory compilers have their limitation— a large memory may need to be implemented with multiple small memories, if generated by memory compilers. In this paper we introduce a testability-driven memory optimizer and wrapper generator that generates BISTed embedded memories by using a commer...

1. Preface This report presents a compressive study on designing memory BIST. The study covers motivation behind memory BIST, algorithm of different test patterns, surveys of current memory BIST architecture, and discussion of various implementation issues. It is my best intention that this report will serve as a knowledge base for future design in memory BIST. The remainder of this report is o...