نتایج جستجو برای: microprocessor chip
تعداد نتایج: 69494 فیلتر نتایج به سال:
| In this paper, we describe the implementation and design methodology of a microprocessor, called HK386. The microprocessor is compatible with Intel 80386 with respect to the behavior of each instruction set. As the extraction of the exact behavior of each instruction set is the single most important step in compatible chip design, we focused our e ort on establishing the reliable veri cation ...
The NVAX CPU chip is a 1.3 million transistor, VAX microprocessor designed in Digital's 0.75-micrometer CMOS-4 technology. It has a typical cycle time of 12 ns under worst-case operating conditions. The goal of the chip design team was to design a high-performance, robust, and reliable chip, within the constraints of a short schedule. Design strategies were developed to achieve this goal, inclu...
A microprocessor implementing IBM S/390 architecture operates in a 10 + 2 way system at frequencies up to 411 MHz (2.43 ns). The chip is fabricated in a 0.2m Le CMOS technology with five layers of metal and tungsten local interconnect. The chip size is 17.35 mm 17.30 mm with about 7.8 million transistors. The power supply is 2.5 V and measured power dissipation at 300 MHz is 37 W. The microproc...
We examine the energy savings possible by re-mapping critical software loops from a microprocessor to configurable logic appearing on the same-chip in commodity chips now commercially available. That logic is typically intended to implement peripherals and coprocessors without increasing chip count – but we show that reduced software energy is an additional benefit, making such chips even more ...
The emphasis in contemporary microprocessor development has been on 8-bit word lengths. Unfortunately, for many applications, the 8-bit microprocessor cannot provide the required accuracy, throughput, programming ease, or flexibility. The ntultichip 16-bit processor has been cost effective in many of these applications, but has provided unused flexibility or speed (at extra cost) in others. Nat...
Real-time support for an iris recognition algorithm is a considerable challenge portable system that commonly used in the field. In this paper, efficient parallel and pipeline architecture design feature extraction template matching processes Ridge Energy Direction (RED) presented. Several techniques proposed to reduce computational complexity while supporting high performance capability includ...
The IBM POWER6e microprocessor chip supports advanced, dynamic power management solutions for managing not just the chip but the entire server. The design facilitates a programmable power management solution for greater flexibility and integration into systemand data-center-wide management solutions. The design of the POWER6 microprocessor provides real-time access to detailed and accurate info...
We describe the design and development of a high-speed 8-channel hybrid integrated optical transceiver package with Clock and Data Recovery (CDR) circuits. The package concept has been developed to be compatible with microprocessor package technology and at the same time allow the integration of low cost, high-performance optical components. A 90nm CMOS optical transceiver chip, 850nm 10Gb/s Ga...
We propose a framework for embedding model predictive control for Systems-on-a-Chip applications. In order to allow the implementation of such a computationally expensive controller on chip, we propose reducing the precision of the operations coupled with using logarithmic number system arithmetic. Two particular control problems are examined. We provide the methodology for choosing the design ...
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