Series-connected thin film piezoelectric elements can generate large output voltages. The output voltage ideally is proportional to the number of connections. However, parasitic capacitances formed by the insulation layers and derived from peripheral circuitry degrade the output voltage. Conventional circuit models are not suitable for predicting the influence of the parasitic capacitance. Ther...

A detailed description and analysis on the behaviour of a bipolar junction transistor in chaotic operation is presented. Bipolar Junction Transistors (BJTs) are basic ingredients of chaotic Colpitts oscillators, which aim at generating chaotic signals for secure communications. The high frequency operation of the chaotic oscillators is a challenging issue due to the parasitic capacitance of the...

A reliable configuration for triggering a series string of power metal oxide semiconductor (MOS) devices without the use of transformer coupling is presented. A capacitor is inserted between the gate and ground of each metal oxide semiconductor field effect transistor (MOSFET), except for the bottom MOSFET in the stack. Using a single input voltage signal to trigger the bottom MOSFET, a voltage...

Silicon carbide (SiC) MOSFET has the potential to replace silicon (Si) IGBT due to its superior switching performance. However due to presence of parasitic inductance in converter layout, device voltage and current experience overshoots and oscillations during device switching. These undesired overshoots increase switching loss. In the context of these parasitic inductances, the performance of ...

The bulk MOSFET scaling has recently encountered significant limitations, mainly related to the gate oxide (SiO2) leakage currents (Gusev et al., 2006; Taur et al., 1997), the large increase of parasitic short channel effects and the dramatic mobility reduction (Fischetti & Laux, 2001) due to highly doped Silicon substrates precisely used to reduce these short channel effects. Technological sol...

Shallow trench isolation (STI) has become the most promising isolation scheme for ULSI applications. However, the trench isolation suffers from dislocations and oxidation induced stacking faults. Such faults are typically located near trench edges. These STI faults increase the junction leakage current and may turn-on the parasitic STI MOSFET resulting in significant leakage current through the...

Due to our limited knowledge about silicon carbide metal–oxide–semiconductor fieldeffect transistors (SiC MOSFETs), the theoretical analysis and change regularity in terms of the effects of temperature on their switching characteristics have not been fully characterized and understood. An analysis of variation in voltage (dVDS/dt) for SiC MOSFET during turn-on and turn-off has been performed th...

In this paper, underlap channel dopant-segregated Schottky barrier (DSSB) SOI MOSFET has been proposed, in which the increased effective channel length (Leff) due to underlap channel at both source/drain (S/D) sides reduces the leakage currents, short-channel effects and the parasitic capacitances as compared to overlap channel DSSB SOI MOSFET. Although in strong inversion the voltage drop acro...

This paper presents a physical explanation of MOSFET intrinsic gate to drain capacitance (CGD) going negative due to Drain Induced Barrier Lowering (DIBL) effect. For the sub-90nm MOS devices, DIBL effect may be dominant enough to guide CGD to negative if de-embedded from parallel extrinsic overlap, outer and inner fringing capacitances. The possibility of this phenomenon is evident from the re...

The methodology for modeling static and dynamic power losses in IGBT MOSFET transistors the Matlab Multisim software environments is given. It shown that when switching processes transistors, / Simulink does not allow determining components of losses, namely, energy turning on transistor, off as well recovery diodes. At same time, simulation diodes Matlab/Simulink carried out with a significant...