Sketch-based algorithms are widely applied in various networking applications. In this paper, we present a compact implementation for on-line traffic change detection on a NetFPGA platform. The system utilizes a straight forward scheme to reveal the key of flow with tradeoff on the accuracy for hardware simplicity. It is capable of digesting traffic up to 4Gbps line rate with accuracy needed ba...

Energy efficiency is an important criterion in the design of next generation networks for both economic and environmental concerns. This paper presents an energy-efficient router that is able to dynamically adapt its routing capability in response to real-time traffic load, achieving energy proportional routing. The NetFPGA reference router, which operates at one of two frequencies (125 MHz or ...

We recently proposed Counter Braids, an SRAM-only counter architecture for high-speed per-flow counting. Accurate per-flow counting was deemed complex and expensive because of the need for large arrays of counters operating at very high link speed (e.g. 40 Gbps). A naive algorithm needs an infeasible amount of SRAM to store both the counters and a flow-to-counter association rule, so that arriv...

Machine learning approaches based on decision trees (DTs) have been proposed for classifying networking traffic. Although this technique has been proven to have the ability to classify encrypted and unknown traffic, the software implementation of DT cannot cope with the current speed of packet traffic. In this paper, hardware architecture of decision tree is proposed on NetFPGA platform. The pr...

High Level Synthesis (HLS) is a promising technology where algorithms described in high level languages are automatically transformed into a hardware design. Although many HLS tools exist, they are mainly targeting developers who want to use a high level programming language to design hardware modules. They are not designed to automatically compile a complete software system, such as a network ...

This paper introduces the Axon, a network device that employs source-routed Ethernet to improve the scalability of local-area networks. Axons provide transparent compatibility with unmodified hosts, which see the network as a single switched Ethernet segment. Prototypes of the Axon have been implemented on the NetFPGA platform and used to demonstrate the performance and backwards compatibility ...

This paper presents (i) Caliper, a highly-accurate packet injection tool, and (ii) NetThreads, a new platform that dramatically simplifies the development of low-level network applications on the NetFPGA board. NetThreads provides a familiar environment to software developers where multithreaded C programs can be compiled and run on the NetFPGA. On top of NetThreads, we have built Caliper, a pr...