Reliance on third-party resources, including thirdparty IP cores and fabrication foundries, as well as wide usage of commercial-off-the-shelf (COTS) components has raised concerns that backdoors and/or hardware Trojans may be inserted into fabricated chips. Defending against hardware backdoors and/or Trojans has primarily focused on detection at various stages in the supply chain. Netlist rever...

Spectral approaches for partitioning netlists that use the eigenvectors of a matrix derived from a weighted graph model of the netlist(hypergraph) have been attracting considerable atttention. There are several known ways in which a weighted graph could be derived from the netlist. However, the effectiveness of these alternate net models for netlist partitioning has remained unexplored. In this...

A five-stage pipelined CPU based on the MIPs ISA is mapped to a self-timed logic family known as Phased Logic (PL). The mapping is performed automatically from a netlist of D-Flip-Flops and 4-input Lookup Tables (LUT4s) to a netlist of Phased Logic gates. Each PL gate implements a 4-input Lookup Table in addition to control logic required for the PL control scheme. PL offers a speedup technique...

The complexity of next-generation VLSI systems will exceed the capabilities of top-down layout synthesis algorithms, particularly in netlist partitioning and module placement. Bottom-up clustering is needed to \condense" the netlist so that the problem size becomes tractable to existing optimization methods. In this paper, we establish the DS quality measure, the rst general metric for evaluati...

This survey describes research directions in netlist partitioning during the past two decades in terms of both problem formulations and solution approaches. We discuss the traditional min-cut and ratio cut bipartitioning formulations along with multi-way extensions and newer problem formulations, e.g., constraint-driven partitioning (for FPGAs) and partitioning with module replication. Our disc...

Authenticated encryption schemes establish both privacy and authenticity. This paper specifies a family of the dedicated authenticated encryption schemes, Artemia. It is an online nonce-based authenticated encryption scheme which supports the associated data. Artemia uses the permutation based mode, JHAE, that is provably secure in the ideal permutation model. The scheme does not require the in...

We present a solution to the veriication problem of high-level synthesis. The high-level synthesis system CALLAS takes as input an algorithmic speciication, in VHDL, and produces as output an EDIF netlist. Both, the speciication and the generated netlist can be interpreted as nite state machine descriptions. Then, in this context, the veriication problem is reduced to proving the behavioral equ...

This application note describes how to alter the printed wiring board (PWB) netlist of a design containing the DS33R11T1/E1/J1 transceiver so that the netlist complies with the Joint Test Action Group (JTAG) specifications. These alterations are necessary because the DS33R11 was designed as a multichip module with multiple die in a single package which cannot be defined by the Boundary-Scan Des...