Recently Network-on-Chip (NoC) technique has been proposed as a promising solution for on-chip interconnection network. However, different interface specification of integrated components raises a considerable difficulty for adopting NoC techniques. In this paper, we present a generic architecture for network interface (NI) and associated wrappers for a networked processor array (NoC based mult...

Network on Chip (NoC) architecture attempts to address different component level architectures with specific interconnection network topologies and routing techniques, some of the topologies are CLICHE, Folded Torus, BFT. Only one distance vector routing used for different topologies. The work has not done with one routing for (CLICHE, Folded Torus and BFT) topologies. In this project we propos...

–As the integration density and complexity of the system-on-Chip (SOC) increases, the conventional interconnects are not suitable to fulfil the demands. The application of traditional network technologies in the form of Network-on-Chip is a possible solution. NoC design space has numerous variables. As an improved topology is selected complexities decrease and power-efficiency increases. In thi...

Network-on-Chip (NoC) is proposed as a new scalable architecture to address the future design challenges of system-ona-chip (SoC). As current verification techniques for on-chip communication algorithms are typically complicated tasks including many hardware modules and software routines, verifying the algorithms themselves is almost impossible. Having the incentive for simplifying verification...

A Scalable hierarchical architecture based Code-Division Multiple Access (CDMA) is proposed for high performance Network-on-Chip (NoC). This hierarchical architecture provides the integration of a large number of IPs in a single on-chip system. The network encoding and decoding schemes for CDMA transmission are provided. The proposed CDMA NoC architecture is compared to the conventional archite...

The Scaling of microchip technologies, from micron to submicron and now to deep sub-micron (DSM) range, has enabled large scale systems-on-chip (SoC). In future deep submicron (DSM) designs, the interconnect effect will definitely dominate performance. Network-on-Chip (NoC) has become a promising solution to bus-based communication infrastructure limitations. NoC designs usually targets Applica...

Network on Chip (NoC) has emerged as a viable solution to the complex communication requirements of constantly evolving System on Chip (SoC). The communication centric architecture of NoC can be optimized across a variety of parameters as per the design requirements. With the development of customized application the inclination has shifted from regular architectures to irregular topology which...

Network-on-Chip (NoC) is an emerging paradigm for communications within large VLSI systems implemented on a single silicon chip. However, the electronic network on chip design faces many problems like energy consumption, bandwidth and QoS. Compared with traditional electronic NoC, optical Network on Chip exhibits advantages of high-bandwidth, low latency and power dissipation. In this paper, a ...

Creating Network on Chip is done here, we present a new network-on-chip (NoC) that handles accurate localizations of the faulty parts of the NoC. The implemented design NoC is based on new error detection mechanisms suitable for dynamic NoCs, where the number and position of processor elements or faulty blocks vary during runtime. Indeed, We designed a online detection of data packet and adapti...

The Network-on-Chip (NoC) approach is a promising solution to the increasing complexity of on-chip communication problems due to its high scalability. A NoC architecture design with ultra-low latency and high throughput is critical in order to support a wide range of applications. In this paper, we propose novel spatial-based NoC resource allocation algorithms to reduce the communication conges...