Multiplication is one of the basic functions used in digital signal processing (DSP). It requires more hardware resources and processing time than addition and subtraction. In fact, 8.72% of all instructions in a typical processing unit is multiplier. The multiplier is a fairly large block of a computing system. The amount of circuitry involved is directly proportional to square of its resoluti...

Multiprecision (MP) reconfigurable multiplier that incorporates variable precision, parallel processing (PP), razor-based dynamic voltage scaling (DVS), and dedicated MP operands scheduling to provide optimum performance for a variety of operating conditions. All the building blocks of the proposed reconfigurable multiplier can either work as independent smallerprecision multipliers or work in ...

A rapid and proficient in power requirement multiplier is always vital in electronics industry like DSP, image processing and ALU in microprocessors. Multiplier is such an imperative block w ith respect to power consumption and area occupied in the system. In order to meet the demand for high speed, various parallel array multiplication algorithms have been proposed by a number of authors. The ...

ÐThis paper presents a design methodology for high-speed Booth encoded parallel multiplier. For partial product generation, we propose a new modified Booth encoding (MBE) scheme to improve the performance of traditional MBE schemes. For final addition, a new algorithm is developed to construct multiple-level conditional-sum adder (MLCSMA). The proposed algorithm can optimize final adder accordi...

In this work a parallel solution method for model predictive control is presented based on the alternating direction multiplier method. Our approach solves the overall problem by decomposing it along the time-axis into smaller subproblem. The resulting subproblems can be solved efficiently in parallel and are coupled by the multiplier update. We specifically considers box constraints, since thi...

High-speed parallel multipliers are one of the keys in RISCs (Reduced Instruction Set Computers), DSPs (Digital Signal Processors), and graphics accelerators and so on. Array multiplier, Booth Multiplier and Wallace Tree multipliers are some of the standard approaches used in implementation of binary multiplier which are suitable for VLSI implementation. A simple digital multiplier (henceforth ...

In this paper a low power and low area array multiplier with carry save adder is proposed. The proposed adder eliminates the final addition stage of the multiplier than the conventional parallel array multiplier. The conventional and proposed multiplier both are synthesized with 16-T full adder. Among Transmission Gate, Transmission Function Adder, 14-T, 16-T full adder shows energy efficiency....

This paper presents serial and parallel hardware units for interval multiplication. Compared to software implementations, these units greatly increase the performance of interval multiplication by providing automatic interval endpoint selection and correct rounding of the results. Area and delay estimates show that compared to a conventional IEEE multiplier, the serial interval multiplier requi...