The realization of a digital phase-locked loop (DPLL) requires to choose a suitable phase detector and to design an appropriate loop filter; these tasks are commonly nontrivial in most applications. In this paper, the phase detector is examined, and a simple model is given to describe the characteristics of the timing function. The DPLL system is then formulated as a state estimation problem; t...

To boost the performance of Large Hadron Collider (LHC) and increase potential discoveries after 2027, High-Luminosity LHC (HL-LHC) project has been announced, with aim increasing luminosity by a factor 10 above design value LHC. This will lead to an pile-up interactions negatively impact reconstruction objects in ATLAS detector, as well its triggering performance. In particular, at forward reg...

In this paper, the performance of two low power phase frequency detectors is compared. A modified D-FF based PFD reduces the power consumption of traditional PFD to 4.732uW at 40MHz clock frequency and dead zone to 40ps.It is suitable for low power applications. A Falling Edge PFD uses only 12 transistors. This PFD operates up to 1GHz at 1.8V supply voltage. It consumes only 5.5uW when operatin...

This paper presents a review of phase locked loop (PLL) techniques. The different types of phase detector, loop filter and oscillators are discussed. It alleviates the problems associated with the classical analog PLL. Linear PLL, Digital PLL and All digital PLL models are implemented in Simulink Simulation results in Simulink gives the performance overview of the three types of PLL. Keywords— ...

This paper presents a novel Phase frequency detector for Charge Pump Phase locked loop (PLL) applications to enable fast frequency acquisition in the phaselocked loop (PLL). To cope with the missing edge problem, the proposed PFD predicts the reset signal and blocks the corresponding input signal during the reset time. The blocked edge is regenerated after the reset signal is deactivated [1]. T...

In previous work, we have shown that second-order phase locked loop (PLL) with sinusoidal phase detector characteristics have a separatrix cycle for a certain value of closed loop gain. It was verified that bifurcation from a stable separatrix cycle is the mechanism responsible for breaking the limit cycle associated with the PLL’s out-of lock state and the loop pulls in (phase lock). The value...

DLL is used as a clock generator due to its stable operation and relatively simple design. Analog DLL has the advantages of lower phase offset and lower clock jitter than digital DLL. However, locking speed is slow in analog DLL. This paper proposes a dual edge triggered phase detector to enhance the locking speed of analog DLL and suggests a closed-form expression of locking speed which can co...