نتایج جستجو برای: power and area consumption

تعداد نتایج: 16965059  

The purpose of this paper is to design a 64×64 bit low power, low delay and high speed Arithmetic Logic Unit (ALU). Arithmetic Logic Unit performs arithmetic operation like addition, multiplication. Adders play important role in ALU. For designing adder, the combination of carry lookahead adder and carry select adder, also add-one circuit have been used to achieve high speed and low area. In mu...

پایان نامه :وزارت علوم، تحقیقات و فناوری - دانشگاه رازی - دانشکده علوم 1391

1. to determine whether difference in birth body mass influenced growth performance in pipistrellus kuhlii we studied a total of 12 captive-born neonates. bats were assigned to two body mass groups: light birth body mass (lbw: 0.89 ± 0.05, n=8) and heavy birth body mass (hbw: 1.35 ± 0.08, n=4). heavier body mass at birth was associated with rapid postnatal growth (body mass and forearm length) ...

A. Naderii A. Pourazar H. Ghasemzadehii M. Aliasgharyii

In this paper, a new structure possessing the advantages of low-power consumption, less hardware and high-speed is proposed for fuzzy controller. The maximum output delay for general fuzzy logic controllers (FLC) is about 86 ns corresponding to 11.63 MFLIPS (fuzzy logic inference per second) while this amount of the delay in the designed fuzzy controller becomes 52ns that corresponds to 19.23 M...

پایان نامه :وزارت علوم، تحقیقات و فناوری - دانشگاه اصفهان - دانشکده علوم 1389

this research concentrates on the lithostratigraphy, biostratigraphy, microfacies and sedimentary environment of the asmari and gachsaran formations at southwest firuzabad. the thickness of the studied section in all 608.95 meters that 220.8 meters belong to the asmari formation and 387.95 meters belong to the gachsaran formation (champe and mol members). in the study area, the asmari formation...

Journal: :International Journal of Computer Applications 2010

2012
Manoj Kumar

In this paper we present a 1 bit Full Adder Cell. It was implemented with lesser number of transistors and lesser power consumption compared to the existing implementations of the Full Adder. Simulations are carried for supply voltages of 1.2v, 0.8v in HSPICE at 0.18μmCMOS technology. Proposed Full Adder results show that there was a reduction of power consumption and efficient in area. Area wa...

پایان نامه :وزارت علوم، تحقیقات و فناوری - پژوهشگاه شیمی و مهندسی شیمی ایران - پژوهشکده شیمی تجزیه و معدنی 1390

hydrochlorothiazide (hct) is a diuretic agent which is shown to be effective in the treatment of hypertension. literature reports have demonstrated that urinary excretion data may be used to assess the bioavailability of various formulations containing this thiazide. also hct consumption by the athletes is one of the drugs which should be regulated by world anti-doping agency (wada), because of...

Journal: :International Journal of VLSI & Signal Processing 2015

2015
Joseph Riad

The trade-offs discussed in the lecture are clear: increasing the inversion level improves speed and area requirement at the expense of increased power consumption. Working in weak inversion helps lower the power consumption but requires larger area and has poor performance in terms of speed. The moderate inversion region exhibits a compromise between speed and area consumption with very little...

Optimizing FPGA architectures is one of the key challenges in digital design flow. Traditionally, FPGA designers make use of CAD tools for evaluating architectures in terms of the area, delay and power. Recently, analytical methods have been proposed to optimize the architectures faster and easier. A complete analytical power, area and delay model have received little attention to date. In addi...

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