In this paper, the implementation of RSA (Rivest, Shamir and Adleman) cryptosystem using Hardware/Software (HW/SW) co-design approach is presented. The main function of RSA is the Modular Exponentiation (ME) which is accomplished by repeated Modular Multiplications (MM’s) on large integers. In this work, we propose the implementation of the ME as a Programmable System on Chip (PSoC), using the ...

This paper gives a brief idea of touch screen technology and its interfacing with a controller to control the speed of single phase induction motor. Here touch screen technology and Programmable System on Chip (PSOC) microcontroller concept is utilized which is less space consumption and easy to design. The aim of this paper is to have remote sensing and speed control of an AC motor.

This paper presents PNETMAP, an algorithm that maps virtual communication networks of a Cyber Physical System onto a partially-known, physical network of reconfigurable embedded systems. The paper describes in detail the algorithm and offers an extensive set of experimental results on the quality of the produced communication structures for different network topologies. Experiments use a networ...

Physiological data acquired during ambulatory health monitoring are affected due to physical movements of limbs. Thus making it important to know about limb movements. We propose a design of a system that can sense the limb movements using several 3-axies accelerometer sensors. The accelerometer sensor signals are acquired in digital form through a programmable system on chip (PSoC) and stored ...

It has been observed that certain char particles shrink when oxidized under kinetically limited conditions, instead of reacting at constant diameter, as expected. This study was perfonned to determine whether or not char from PSOC 1451 coal, prepared at different temperatures would also shrink during low temperature gasification. Coal chars, formed at l 200K and 1600K, were levitated in the ele...

The use of deep learning solutions in different disciplines is increasing and their algorithms are computationally expensive most cases. For this reason, numerous hardware accelerators have appeared to compute operations efficiently parallel, achieving higher performance lower latency. These need large amounts data feed each computing layers, which makes it necessary handle the transfers that c...

In this paper, a methodology for designing reconfigurable discrete-time ∆Σ modulator topologies is proposed. Topologies are generated from a set of all possible topologies expressed by a generic topology, and optimized for minimizing the complexity of the topologies, maximizing the topology robustness with respect to circuit nonidealities, and minimizing total power consumption. The paper prese...